On Thu, 7 Mar 2019 17:01:36 +1100, Matthew Donald wrote: >Describing memory as the new disk is quite apt. > >A given instruction may take between zero and hundreds of thousands of >clocks. Z10 and later processors execute upto 11 instructions in parallel, >although they rarely exceed three. > >The key bottle neck is operand access times. L1 cache costs 1 clock cycle. >L2 costs 7 clocks. L3 is 60 clocks and L4 is 600. A simple main memory >access (assuming a TLB hit otherwise there may be 2 further memory accesses >to look up the page table) will take 2000 clocks. If the operand is in a CF >storage structure which is part of a GDPS Plex then access may take >hundreds of thousands of clocks. > Don't forget page faults.
Given the uncertainty in instruction timing, how can companies author Service Level Agreements? I once used a site with a CDC 6400 where the DP manager tried mightily, for chargeback purposes, to make resource accounting repeatable regardless of background loading. Failed. -- gil ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
