On Thu, 07 Oct 2010 23:55:38 +0100 Chris Wilson <[email protected]> wrote:
> On Thu, 7 Oct 2010 15:48:14 -0700, Bryan Freed <[email protected]> wrote: > > The time between start of the pixel clock and backlight enable is a basic > > panel timing constraint. If no VBIOS Table is found, and the Panel Power > > On/Off registers are found to be 0, assume we are booting without VBIOS > > initialization and set these registers to something reasonable. > > IIRC, the panel sequence registers are meant to be stored in the VBIOS. So > if we add the parsing of those to the driver and add the defaults to > init_vbt_default() then we can check whether PP_ON_DELAYS is valid upon > device init (module load and resume) and fixup in case the BIOS does not. Right, those values should be in the VBT. Getting them wrong can actually damage your panel, so we need to take care here. The whole point of the power sequencing logic and register lock is to avoid such damage. That said, I've abused my panels (both LVDS and eDP) pretty hard and have yet to damage one in any visible way, so stealing some conservative (i.e. long) delays from an existing VBT will probably work ok. -- Jesse Barnes, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
