On Thu, 7 Oct 2010 15:48:14 -0700, Bryan Freed <[email protected]> wrote: > The time between start of the pixel clock and backlight enable is a basic > panel timing constraint. If no VBIOS Table is found, and the Panel Power > On/Off registers are found to be 0, assume we are booting without VBIOS > initialization and set these registers to something reasonable.
IIRC, the panel sequence registers are meant to be stored in the VBIOS. So if we add the parsing of those to the driver and add the defaults to init_vbt_default() then we can check whether PP_ON_DELAYS is valid upon device init (module load and resume) and fixup in case the BIOS does not. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
