Move RC6 enable after we reset rings for all regines, as RC6 on Sandybridge would setup ring idle state, so I assume we should have setup rings already.
Signed-off-by: Zhenyu Wang <[email protected]> --- drivers/gpu/drm/i915/i915_drv.c | 4 ++++ drivers/gpu/drm/i915/i915_suspend.c | 3 --- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index a55b71d..b40f3ee 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -384,6 +384,10 @@ static int i915_drm_thaw(struct drm_device *dev) if (IS_IRONLAKE_M(dev)) ironlake_enable_rc6(dev); + + if (IS_GEN6(dev)) + gen6_enable_rps(dev_priv); + } intel_opregion_init(dev); diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index 26387c3..8e6aa8c 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c @@ -862,9 +862,6 @@ int i915_restore_state(struct drm_device *dev) intel_init_emon(dev); } - if (IS_GEN6(dev)) - gen6_enable_rps(dev_priv); - /* Memory arbitration state */ if (IS_GEN3(dev)) I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000); -- 1.7.4.1 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
