On Mon, 21 Mar 2011 17:27:15 +0800 Zhenyu Wang <[email protected]> wrote:
> we don't use it anywhere. > > Signed-off-by: Zhenyu Wang <[email protected]> > --- > drivers/gpu/drm/i915/i915_suspend.c | 6 ------ > 1 files changed, 0 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_suspend.c > b/drivers/gpu/drm/i915/i915_suspend.c > index 7f00f8b..11e61a3 100644 > --- a/drivers/gpu/drm/i915/i915_suspend.c > +++ b/drivers/gpu/drm/i915/i915_suspend.c > @@ -819,9 +819,6 @@ int i915_save_state(struct drm_device *dev) > if (IS_GEN6(dev)) > gen6_disable_rps(dev); > > - /* Cache mode state */ > - dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); > - > /* Memory Arbitration state */ > dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE); > > @@ -867,9 +864,6 @@ int i915_restore_state(struct drm_device *dev) > if (IS_GEN6(dev)) > gen6_enable_rps(dev_priv); > > - /* Cache mode state */ > - I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000); > - > /* Memory arbitration state */ > I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000); I'd be fine with this if we actually set CACHE_MODE_0 to a reasonable value somewhere else. But right now we rely on the BIOS settings and for the BIOS to reprogram it at resume, which may or may not be reliable. -- Jesse Barnes, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
