On Wed, 30 Mar 2011 14:45:11 -0700, Eric Anholt <[email protected]> wrote: > On Wed, 30 Mar 2011 18:16:11 +0100, Chris Wilson <[email protected]> > wrote: > > On Wed, 30 Mar 2011 09:59:55 -0700, Eric Anholt <[email protected]> wrote: > > > And what about a CPU write through the GTT? > > > > Even on SNB these are still UC. And we should try hard not to, as the > > specs give dire warnings about writing to snooped PTEs through the GTT. > > (Since we will bypass the caches with the write, aiui, and cause > > confusion.) > > Oh, wow. That's really bad. Reject this series if so.
I plucked that tidbit out of the specs for the BLT engine, which has not been rigorously updated since gen2... Though don't we also encounter a few subtleties with movnta (__copy_from_user_nocache_nozero from pwrite) and data in cachelines? But it is something that I worry about given my desire to start mapping user pages and using the BLT engine for C to UC transfers. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
