On Wed, 15 Jun 2011 23:32:33 +0200 Jesse Barnes <[email protected]> wrote:
> Per the specs and to address > https://bugs.freedesktop.org/show_bug.cgi?id=36888. > > Signed-off-by: Jesse Barnes <[email protected]> > --- > drivers/gpu/drm/i915/intel_display.c | 8 ++++++-- > 1 files changed, 6 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index 81a9059..03ce9fa 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -2699,14 +2699,18 @@ static void ironlake_crtc_enable(struct drm_crtc > *crtc) > I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size); > } > > + /* > + * On ILK+ LUT must be loaded before the pipe is running but with > + * clocks enabled > + */ > + intel_crtc_load_lut(crtc); > + > intel_enable_pipe(dev_priv, pipe, is_pch_port); > intel_enable_plane(dev_priv, plane, pipe); > > if (is_pch_port) > ironlake_pch_enable(crtc); > > - intel_crtc_load_lut(crtc); > - > mutex_lock(&dev->struct_mutex); > intel_update_fbc(dev); > mutex_unlock(&dev->struct_mutex); Keith, please pull this one in for 3.1. Hardware will wedge if we try to access the palette after pipe enable but before FDI or eDP training completes, so we may as well just do it right before pipe enable. Thanks, -- Jesse Barnes, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
