On Fri, 23 Sep 2011 08:23:14 -0700, Ben Widawsky <[email protected]> wrote: > On Fri, 23 Sep 2011 11:21:29 +0100 > Chris Wilson <[email protected]> wrote: > > > On SandyBridge in order to receive an event on the RENDER ring, you > > first must unmask the corresponding bit in the DERRMR (Display Engine > > Render Response Mask Register). This register is not accessible from a > > non-secure MI_LOAD_REGISTER_IMM so resort to unmasking all events upon > > initialisation. Presumably this leads to an undesirable increase in > > PCI traffic (possibly 4 additional wakeups per vblank per active > > pipe). > > > > More tricky solutions include extending EXECBUFFER to include a > > request to enable the appropriate render response and for the kernel > > to unmask and reset around the batch. Also we need to include a flag > > to indicate that it is safe to use MI_WAIT_FOR_EVENT as well. > > > > Signed-off-by: Chris Wilson <[email protected]> > > --- > > Sounds good, but... > > {WA} Do not cause more than one display event to be reported in the render > response. Either mask off all but one event, unmasking one bit in this > register, or never initiate more than one event.
Dear HW Engineers, I hate you all, Thanks. Looks like we need a more tricksy solution then. I'm pretty sure that I can't write to that register from the ring either, but that is the only sane idea I've had. But this means I can't vsync output to both pipes which is also sad. And to think this morning I was enjoying tear-free video at last on SNB. :( -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
