Very ugly hack,
In file ---> intel_display.c function --- >
ironlake_crtc_mode_set
temp = I915_READ(_TRANSACONF); I915_WRITE(_TRANSACONF, temp &
~(7<<21));
I915_WRITE( 0x60028, 0x00000000); //VSYNCSHIFT_A— Vertical Sync Shift
Register This register needs to be 0x00000000 for progressive mode
I915_WRITE(PIPECONF(pipe), pipeconf); POSTING_READ(PIPECONF(pipe));
In file ---> i915_reg.h #define
PIPECONF_INTERLACE_W_FIELD_INDICATION (7 << 21) // ( 6 << 21)
Not sure why the PIPECONF MASK is 110 and not 111, from intel pdf 000b
Progressive Fetch / Progressive display / 001b PF-ID Progressive Fetch /
Interlaced display (HDMI) Requires panel fitting to be enabled
Next will be to solve the RGB problem i have.
From: [email protected]
To: [email protected]
Date: Tue, 24 Jan 2012 20:38:57 +0000
Subject: Re: [Intel-gfx] [PROBLEM FOUND] Problem No HDMI when AV/TV in standby
mode
Hello all,
I think i have found why there is a problem with my Onkyo AV when the TV/AV are
in standby mode.
I run the following test.
Boot PC with AV/TV in standby and dump intel registers to a file TEST1Boot PC
with AV/TV on and dump intel register to file TEST2Using the diff to find the
difference between both files i found the following:
root@SERVER:~# diff test1 test214c14< PIPEACONF:
0xc0200000 (enabled, active, 8bpc)---> PIPEACONF:
0xc0000000 (enabled, active, 8bpc)21c21< VSYNCSHIFT_A:
0x0000038c---> VSYNCSHIFT_A: 0x00000000125c125<
TRANSACONF: 0xc0600000 (enable, active)--->
TRANSACONF: 0xc0000000 (enable, active)
So register PIPEACONF, VSYNCSHIFT_A and TRANSACONF are different. By checking
intel documentation i found that this registers are responsibly for setting up
the progressive/interleave mode. As so im thinking that this registers are not
being reinitialize or cleaned.
Is this possible?
Since im up for one more test i used intel_reg_read/write to modified the
registers and correct the values, to my surprise after writing to all the
register the AV shows my desktop correctly.
My other question is if they need to be reinitialized where in the code shall
this be done? I'm up for writing a small patch to fix this issue, just need
some one to point me on the right direction.
Thanks--Paulo Louro
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
