Like in this patch, the defines indentation in some patches in this series sounds strange, wrong, or at least different from the one already in use.
So, since I don't know if we should care about indentation now, for those patches I'll just mark like this: * indentation Reviewed-by: Rodrigo Vivi <[email protected]> On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov <[email protected]> wrote: > This defines the registers used by different power wells. > > Signed-off-by: Eugeni Dodonov <[email protected]> > --- > drivers/gpu/drm/i915/i915_reg.h | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 52a06be..ddc9c87 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3850,4 +3850,17 @@ > #define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16) > #define AUD_CONFIG_DISABLE_NCTS (1 << 3) > > +/* HSW Power Wells */ > +#define HSW_PWR_WELL_CTL1 0x45400 /* BIOS */ > +#define HSW_PWR_WELL_CTL2 0x45404 /* Driver */ > +#define HSW_PWR_WELL_CTL3 0x45408 /* KVMR */ > +#define HSW_PWR_WELL_CTL4 0x4540C /* Debug */ > +#define HSW_PWR_WELL_ENABLE (1<<31) > +#define HSW_PWR_WELL_STATE (1<<30) > +#define HSW_PWR_WELL_CTL5 0x45410 > +#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31) > +#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20) > +#define HSW_PWR_WELL_FORCE_ON (1<<19) > +#define HSW_PWR_WELL_CTL6 0x45414 > + > #endif /* _I915_REG_H_ */ > -- > 1.7.9.2 > > _______________________________________________ > Intel-gfx mailing list > [email protected] > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Rodrigo Vivi Blog: http://blog.vivi.eng.br GPG: 0x905BE242 @ wwwkeys.pgp.net _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
