On Thu, 29 Mar 2012 19:11:26 -0700, Ben Widawsky <[email protected]> wrote: > - gen6 put/get only need one argument > rflags and gflags are always the same (see above explanation) > - remove a couple redundantly defined IRQs > - reordered some lines to make things go in descending order > > Every ring has its own interrupts, enables, masks, and status bits that > are fed into the main interrupt enable/mask/status registers. At one > point in time it seemed like a good idea to make our functions support > the notion that each interrupt may have a different bit position in the > corresponding register (blitter parser error may be bit n in IMR, but > bit m in blitter IMR). It turned out though that the HW designers did us > a solid on Gen6+ and this unfortunate situation has been avoided. This > allows our interrupt code to be cleaned up a bit. > > I jammed this into one commit because there should be no functional > change with this commit, and staging it into multiple commits was > unnecessarily artificial IMO. > > CC: Chris Wilson <[email protected]> > CC: Jesse Barnes <[email protected]> > Signed-off-by: Ben Widawsky <[email protected]>
Those two patches are Reviewed-by: Chris Wilson <[email protected]> We can go further in simplifying get/put irq. First requires a dev_priv->gt.enable_irq() and then refactor the common (pro|epi)logue. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
