On Fri, 13 Apr 2012 15:51:51 +0200, Daniel Vetter <[email protected]>
wrote:
> ... we will botch up the bit17 swizzling. Furthermore tiled pwrite is
> a (now) unused slowpath, so no one really cares.
>
> This fixes the last swizzling issues I have with i-g-t on my bit17
> swizzling i915G. No regression, it's been broken since the dawn of
> gem, but it's nice for regression tracking when really _all_ i-g-t
> tests work.
>
> Signed-Off-by: Daniel Vetter <[email protected]>
> ---
> drivers/gpu/drm/i915/i915_gem.c | 1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 71934dd..9415c07 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -876,6 +876,7 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
>
> if (obj->gtt_space &&
> obj->cache_level == I915_CACHE_NONE &&
> + obj->tiling_mode == I915_TILING_NONE &&
> obj->map_and_fenceable &&
> obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
> ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
static inline int i915_gem_object_swizzle(struct drm_i915_gem_object *obj)
{
struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
switch (obj->tiling_mode) {
default:
case I915_TILING_NONE: return I915_BIT_6_SIZZLE_NONE;
case I915_TILING_X: return dev_priv->mm.bit_6_swizzle_x;
case I915_TILING_Y: return dev_priv->mm.bit_6_swizzle_y;
}
}
And share with i915_gem_tiling.c. Or is that overkill?
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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