From: Tom O'Rourke <Tom.O'rou...@intel.com>
Adds debugfs hooks for enabling/disabling each slpc task.
The enable/disable debugfs files are
i915_slpc_gtperf, i915_slpc_balancer, and i915_slpc_dcc.
Each of these can take the values:
"default", "enabled", or "disabled"
v1: update for SLPC v2015.2.4
dfps and turbo merged and renamed "gtperf"
ibc split out and renamed "balancer"
Avoid magic numbers (Jon Bloomfield)
v2-v3: Rebase.
v5: Moved slpc_enable_disable_set and slpc_enable_disable_get to
intel_slpc.c. s/slpc_enable_disable_get/intel_slpc_task_status
and s/slpc_enable_disable_set/intel_slpc_task_control. Prepared
separate functions to update the task status only in the SLPC
shared memory. Passing dev_priv as parameter.
Signed-off-by: Tom O'Rourke <Tom.O'rou...@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 184 ++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_slpc.c | 88 +++++++++++++++++
drivers/gpu/drm/i915/intel_slpc.h | 9 ++
3 files changed, 281 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 8461c33..87d83d7 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1071,6 +1071,187 @@ static ssize_t i915_error_state_read(struct file *file,
char __user *userbuf,
i915_next_seqno_get, i915_next_seqno_set,
"0x%llx\n");
+static void slpc_param_show(struct seq_file *m, u32 enable_id, u32 disable_id)
+{
+ struct drm_i915_private *dev_priv = m->private;
+ const char *status;
+ u64 val;
+ int ret;
+
+ ret = intel_slpc_task_status(dev_priv, &val, enable_id, disable_id);
+
+ if (ret) {
+ seq_printf(m, "error %d\n", ret);
+ } else {
+ switch (val) {
+ case SLPC_PARAM_TASK_DEFAULT:
+ status = "default\n";
+ break;
+
+ case SLPC_PARAM_TASK_ENABLED:
+ status = "enabled\n";
+ break;
+
+ case SLPC_PARAM_TASK_DISABLED:
+ status = "disabled\n";
+ break;
+
+ default:
+ status = "unknown\n";
+ break;
+ }
+
+ seq_puts(m, status);
+ }
+}
+
+static int slpc_param_write(struct seq_file *m, const char __user *ubuf,
+ size_t len, u32 enable_id, u32 disable_id)
+{
+ struct drm_i915_private *dev_priv = m->private;
+ u64 val;
+ int ret = 0;
+ char buf[10];
+
+ if (len >= sizeof(buf))
+ ret = -EINVAL;
+ else if (copy_from_user(buf, ubuf, len))
+ ret = -EFAULT;
+ else
+ buf[len] = '\0';
+
+ if (!ret) {
+ if (!strncmp(buf, "default", 7))
+ val = SLPC_PARAM_TASK_DEFAULT;
+ else if (!strncmp(buf, "enabled", 7))
+ val = SLPC_PARAM_TASK_ENABLED;
+ else if (!strncmp(buf, "disabled", 8))
+ val = SLPC_PARAM_TASK_DISABLED;
+ else
+ ret = -EINVAL;
+ }
+
+ if (!ret)
+ ret = intel_slpc_task_control(dev_priv, val, enable_id,
+ disable_id);
+
+ return ret;
+}
+
+static int slpc_gtperf_show(struct seq_file *m, void *data)
+{
+ slpc_param_show(m, SLPC_PARAM_TASK_ENABLE_GTPERF,
+ SLPC_PARAM_TASK_DISABLE_GTPERF);
+
+ return 0;
+}
+
+static int slpc_gtperf_open(struct inode *inode, struct file *file)
+{
+ struct drm_i915_private *dev_priv = inode->i_private;
+
+ return single_open(file, slpc_gtperf_show, dev_priv);
+}
+
+static ssize_t slpc_gtperf_write(struct file *file, const char __user *ubuf,
+ size_t len, loff_t *offp)
+{
+ struct seq_file *m = file->private_data;
+ int ret = 0;
+
+ ret = slpc_param_write(m, ubuf, len, SLPC_PARAM_TASK_ENABLE_GTPERF,
+ SLPC_PARAM_TASK_DISABLE_GTPERF);
+ if (ret)
+ return ret;
+
+ return len;
+}
+
+static const struct file_operations i915_slpc_gtperf_fops = {
+ .owner = THIS_MODULE,
+ .open = slpc_gtperf_open,
+ .release = single_release,
+ .read = seq_read,
+ .write = slpc_gtperf_write,
+ .llseek = seq_lseek
+};
+
+static int slpc_balancer_show(struct seq_file *m, void *data)
+{
+ slpc_param_show(m, SLPC_PARAM_TASK_ENABLE_BALANCER,
+ SLPC_PARAM_TASK_DISABLE_BALANCER);
+
+ return 0;
+}
+
+static int slpc_balancer_open(struct inode *inode, struct file *file)
+{
+ struct drm_i915_private *dev_priv = inode->i_private;
+
+ return single_open(file, slpc_balancer_show, dev_priv);
+}
+
+static ssize_t slpc_balancer_write(struct file *file, const char __user *ubuf,
+ size_t len, loff_t *offp)
+{
+ struct seq_file *m = file->private_data;
+ int ret = 0;
+
+ ret = slpc_param_write(m, ubuf, len, SLPC_PARAM_TASK_ENABLE_BALANCER,
+ SLPC_PARAM_TASK_DISABLE_BALANCER);
+ if (ret)
+ return ret;
+
+ return len;
+}
+
+static const struct file_operations i915_slpc_balancer_fops = {
+ .owner = THIS_MODULE,
+ .open = slpc_balancer_open,
+ .release = single_release,
+ .read = seq_read,
+ .write = slpc_balancer_write,
+ .llseek = seq_lseek
+};
+
+static int slpc_dcc_show(struct seq_file *m, void *data)
+{
+ slpc_param_show(m, SLPC_PARAM_TASK_ENABLE_DCC,
+ SLPC_PARAM_TASK_DISABLE_DCC);
+
+ return 0;
+}
+
+static int slpc_dcc_open(struct inode *inode, struct file *file)
+{
+ struct drm_i915_private *dev_priv = inode->i_private;
+
+ return single_open(file, slpc_dcc_show, dev_priv);
+}
+
+static ssize_t slpc_dcc_write(struct file *file, const char __user *ubuf,
+ size_t len, loff_t *offp)
+{
+ struct seq_file *m = file->private_data;
+ int ret = 0;
+
+ ret = slpc_param_write(m, ubuf, len, SLPC_PARAM_TASK_ENABLE_DCC,
+ SLPC_PARAM_TASK_DISABLE_DCC);
+ if (ret)
+ return ret;
+
+ return len;
+}
+
+static const struct file_operations i915_slpc_dcc_fops = {
+ .owner = THIS_MODULE,
+ .open = slpc_dcc_open,
+ .release = single_release,
+ .read = seq_read,
+ .write = slpc_dcc_write,
+ .llseek = seq_lseek
+};
+
static int i915_frequency_info(struct seq_file *m, void *unused)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -5480,6 +5661,9 @@ static int i915_debugfs_create(struct dentry *root,
const struct file_operations *fops;
} i915_debugfs_files[] = {
{"i915_wedged", &i915_wedged_fops},
+ {"i915_slpc_gtperf", &i915_slpc_gtperf_fops},
+ {"i915_slpc_balancer", &i915_slpc_balancer_fops},
+ {"i915_slpc_dcc", &i915_slpc_dcc_fops},
{"i915_max_freq", &i915_max_freq_fops},
{"i915_min_freq", &i915_min_freq_fops},
{"i915_cache_sharing", &i915_cache_sharing_fops},
diff --git a/drivers/gpu/drm/i915/intel_slpc.c
b/drivers/gpu/drm/i915/intel_slpc.c
index 2f7fe8f..0440f85 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -216,6 +216,94 @@ void intel_slpc_get_param(struct drm_i915_private
*dev_priv,
kunmap_atomic(data);
}
+int slpc_mem_task_control(struct slpc_shared_data *data, u64 val,
+ u32 enable_id, u32 disable_id)
+{
+ int ret = 0;
+
+ if (val == SLPC_PARAM_TASK_DEFAULT) {
+ /* set default */
+ slpc_mem_unset_param(data, enable_id);
+ slpc_mem_unset_param(data, disable_id);
+ } else if (val == SLPC_PARAM_TASK_ENABLED) {
+ /* set enable */
+ slpc_mem_set_param(data, enable_id, 1);
+ slpc_mem_unset_param(data, disable_id);
+ } else if (val == SLPC_PARAM_TASK_DISABLED) {
+ /* set disable */
+ slpc_mem_set_param(data, disable_id, 1);
+ slpc_mem_unset_param(data, enable_id);
+ } else {
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+
+int intel_slpc_task_control(struct drm_i915_private *dev_priv, u64 val,
+ u32 enable_id, u32 disable_id)
+{
+ int ret = 0;
+
+ if (!dev_priv->guc.slpc.active) {
+ ret = -ENODEV;
+ } else if (val == SLPC_PARAM_TASK_DEFAULT) {
+ /* set default */
+ intel_slpc_unset_param(dev_priv, enable_id);
+ intel_slpc_unset_param(dev_priv, disable_id);
+ } else if (val == SLPC_PARAM_TASK_ENABLED) {
+ /* set enable */
+ intel_slpc_set_param(dev_priv, enable_id, 1);
+ intel_slpc_unset_param(dev_priv, disable_id);
+ } else if (val == SLPC_PARAM_TASK_DISABLED) {
+ /* set disable */
+ intel_slpc_set_param(dev_priv, disable_id, 1);
+ intel_slpc_unset_param(dev_priv, enable_id);
+ } else {
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+
+int intel_slpc_task_status(struct drm_i915_private *dev_priv, u64 *val,
+ u32 enable_id, u32 disable_id)
+{
+ int override_enable, override_disable;
+ u32 value_enable, value_disable;
+ int ret = 0;
+
+ if (!dev_priv->guc.slpc.active) {
+ ret = -ENODEV;
+ } else if (val) {
+ intel_slpc_get_param(dev_priv, enable_id, &override_enable,
+ &value_enable);
+ intel_slpc_get_param(dev_priv, disable_id, &override_disable,
+ &value_disable);
+
+ /*
+ * Set the output value:
+ * 0: default
+ * 1: enabled
+ * 2: disabled
+ * 3: unknown (should not happen)
+ */
+ if (override_disable && (value_disable == 1))
+ *val = SLPC_PARAM_TASK_DISABLED;
+ else if (override_enable && (value_enable == 1))
+ *val = SLPC_PARAM_TASK_ENABLED;
+ else if (!override_enable && !override_disable)
+ *val = SLPC_PARAM_TASK_DEFAULT;
+ else
+ *val = SLPC_PARAM_TASK_UNKNOWN;
+
+ } else {
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+
void intel_slpc_init(struct drm_i915_private *dev_priv)
{
struct intel_guc *guc = &dev_priv->guc;
diff --git a/drivers/gpu/drm/i915/intel_slpc.h
b/drivers/gpu/drm/i915/intel_slpc.h
index 2cecdc8..c373f39 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -222,6 +222,11 @@ enum slpc_param_id {
SLPC_MAX_PARAM,
};
+#define SLPC_PARAM_TASK_DEFAULT 0
+#define SLPC_PARAM_TASK_ENABLED 1
+#define SLPC_PARAM_TASK_DISABLED 2
+#define SLPC_PARAM_TASK_UNKNOWN 3
+
/* intel_slpc.c */
void intel_slpc_init(struct drm_i915_private *dev_priv);
void intel_slpc_cleanup(struct drm_i915_private *dev_priv);
@@ -238,5 +243,9 @@ void intel_slpc_get_param(struct drm_i915_private
*dev_priv, u32 id,
int *overriding, u32 *value);
int intel_slpc_max_freq_set(struct drm_i915_private *dev_priv, u32 val);
int intel_slpc_min_freq_set(struct drm_i915_private *dev_priv, u32 val);
+int intel_slpc_task_control(struct drm_i915_private *dev_priv, u64 val,
+ u32 enable_id, u32 disable_id);
+int intel_slpc_task_status(struct drm_i915_private *dev_priv, u64 *val,
+ u32 enable_id, u32 disable_id);
#endif
--
1.9.1
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