On Wed, Dec 28, 2016 at 11:27:37AM +0000, Chris Wilson wrote: > The GuC uses a special mapping for the upper end of the Global GTT, > similar to the way it uses a special mapping for the lower end, so > exclude it from our drm_mm to prevent us using it. > > v2: Rename to reflect that it is unmappable similar to the region at the > bottom of the GGTT, and couple it into the assertion that we don't feed > unmappable addresses to the GuC. > > Signed-off-by: Chris Wilson <[email protected]> > Cc: Michal Wajdeczko <[email protected]> > Cc: Arkadiusz Hiler <[email protected]> > Cc: Daniele Ceraolo Spurio <[email protected]> > --- > drivers/gpu/drm/i915/i915_gem_gtt.c | 10 ++++++++++ > drivers/gpu/drm/i915/i915_guc_reg.h | 3 +++ > drivers/gpu/drm/i915/intel_uc.h | 1 + > 3 files changed, 14 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c > b/drivers/gpu/drm/i915/i915_gem_gtt.c > index 6af9311f72f5..bc2b4421cbd6 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -3176,6 +3176,16 @@ int i915_ggtt_probe_hw(struct drm_i915_private > *dev_priv) > if (ret) > return ret; > > + /* Trim the GGTT to fit the GuC mappable upper range (when enabled). > + * This is easier than doing range restriction on the fly, as we > + * currently don't have any bits spare to pass in this upper > + * restriction! > + */ > + if (HAS_GUC(dev_priv) && i915.enable_guc_loading) { > + ggtt->base.total = min_t(u64, ggtt->base.total, GUC_GGTT_TOP); > + ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total); > + } > + > if ((ggtt->base.total - 1) >> 32) { > DRM_ERROR("We never expected a Global GTT with more than 32bits" > " of address space! Found %lldM!\n", > diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h > b/drivers/gpu/drm/i915/i915_guc_reg.h > index 5e638fc37208..6a0adafe0523 100644 > --- a/drivers/gpu/drm/i915/i915_guc_reg.h > +++ b/drivers/gpu/drm/i915/i915_guc_reg.h > @@ -73,6 +73,9 @@ > #define GUC_WOPCM_TOP (0x80 << 12) /* 512KB */ > #define BXT_GUC_WOPCM_RC6_RESERVED (0x10 << 12) /* 64KB */ > > +/* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */ > +#define GUC_GGTT_TOP 0xFEE00000 > + > #define GEN8_GT_PM_CONFIG _MMIO(0x138140) > #define GEN9LP_GT_PM_CONFIG _MMIO(0x138140) > #define GEN9_GT_PM_CONFIG _MMIO(0x13816c) > diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h > index d556215e691f..c594472d918b 100644 > --- a/drivers/gpu/drm/i915/intel_uc.h > +++ b/drivers/gpu/drm/i915/intel_uc.h > @@ -204,6 +204,7 @@ static inline u32 guc_ggtt_offset(struct i915_vma *vma) > { > u32 offset = i915_ggtt_offset(vma); > GEM_BUG_ON(offset < GUC_WOPCM_TOP); > + GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
range_overflows is not yet visible to this header. :| -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
