Chris Wilson <[email protected]> writes: > Mark when we run the execlist tasklet following the interrupt, so we > don't probe a potentially uninitialised register when submitting the > contexts multiple times before the hardware responds. > > v2: Use a shared engine->irq_posted > v3: Always use locked bitops to be sure of atomicity wrt to other bits > in the mask. > > Signed-off-by: Chris Wilson <[email protected]> > Cc: Mika Kuoppala <[email protected]> > Cc: Tvrtko Ursulin <[email protected]
Missing '>' from Cc. Reviewed-by: Mika Kuoppala <[email protected]> > --- > drivers/gpu/drm/i915/i915_irq.c | 7 +++++-- > drivers/gpu/drm/i915/intel_lrc.c | 3 ++- > drivers/gpu/drm/i915/intel_ringbuffer.h | 1 + > 3 files changed, 8 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 7e087c344265..3f3c9082b0f8 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -1349,8 +1349,11 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, > u32 iir, int test_shift) > { > if (iir & (GT_RENDER_USER_INTERRUPT << test_shift)) > notify_ring(engine); > - if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift)) > - tasklet_schedule(&engine->irq_tasklet); > + > + if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift)) { > + set_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); > + tasklet_hi_schedule(&engine->irq_tasklet); > + } > } > > static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv, > diff --git a/drivers/gpu/drm/i915/intel_lrc.c > b/drivers/gpu/drm/i915/intel_lrc.c > index 9896027880ea..f729568e5e54 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -564,7 +564,7 @@ static void intel_lrc_irq_handler(unsigned long data) > > intel_uncore_forcewake_get(dev_priv, engine->fw_domains); > > - if (!execlists_elsp_idle(engine)) { > + while (test_and_clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted)) { > u32 __iomem *csb_mmio = > dev_priv->regs + > i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)); > u32 __iomem *buf = > @@ -1297,6 +1297,7 @@ static int gen8_init_common_ring(struct intel_engine_cs > *engine) > DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name); > > /* After a GPU reset, we may have requests to replay */ > + clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); > if (!execlists_elsp_idle(engine)) { > engine->execlist_port[0].count = 0; > engine->execlist_port[1].count = 0; > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h > b/drivers/gpu/drm/i915/intel_ringbuffer.h > index a9ea84ea3155..8e872730f8eb 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.h > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h > @@ -213,6 +213,7 @@ struct intel_engine_cs { > > unsigned long irq_posted; > #define ENGINE_IRQ_BREADCRUMB 0 > +#define ENGINE_IRQ_EXECLIST 1 > > /* Rather than have every client wait upon all user interrupts, > * with the herd waking after every interrupt and each doing the > -- > 2.11.0 > > _______________________________________________ > Intel-gfx mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
