Looks ok.
Acked-by: Mika Kahola <mika.kah...@intel.com>
On Wed, 2017-01-25 at 19:43 +0530, Vidya Srinivas wrote:
> From: Uma Shankar <uma.shan...@intel.com>
>
> Enable MIPI IO WA for BXT DSI as per bspec and
> program the DSI regulators.
>
> v2: Moved IO enable to pre-enable as per Mika's
> review comments. Also reused the existing register
> definition for BXT_P_CR_GT_DISP_PWRON.
>
> v3: Added Programming the DSI regulators as per disable/enable
> sequences.
>
> v4: Restricting regulator changes to BXT as suggested by
> Jani/Mika
>
> v5: Removed redundant read/modify for regulator register as
> per Jani's comment. Maintain enable/disable symmetry as per spec.
>
> Signed-off-by: Uma Shankar <uma.shan...@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srini...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
> drivers/gpu/drm/i915/intel_dsi.c | 24 ++++++++++++++++++++++++
> 2 files changed, 31 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 00970aa..0a9ad44 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1553,6 +1553,7 @@ enum skl_disp_power_wells {
> _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))
>
> #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
> +#define MIPIO_RST_CTRL (1 << 2)
>
> #define _BXT_PHY_CTL_DDI_A 0x64C00
> #define _BXT_PHY_CTL_DDI_B 0x64C10
> @@ -8301,6 +8302,12 @@ enum {
> #define _BXT_MIPIC_PORT_CTRL 0x6B8C0
> #define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc,
> _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)
>
> +#define BXT_P_DSI_REGULATOR_CFG _MMIO(0x16002
> 0)
> +#define STAP_SELECT (1 << 0)
> +
> +#define BXT_P_DSI_REGULATOR_TX_CTRL _MMIO(0x160054)
> +#define HS_IO_CTRL_SELECT (1 << 0)
> +
> #define DPI_ENABLE (1 << 31)
> /* A + C */
> #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
> #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> b/drivers/gpu/drm/i915/intel_dsi.c
> index 16732e7..c98234e 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -548,6 +548,7 @@ static void intel_dsi_pre_enable(struct
> intel_encoder *encoder,
> struct drm_i915_private *dev_priv = to_i915(encoder-
> >base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder-
> >base);
> enum port port;
> + u32 val;
>
> DRM_DEBUG_KMS("\n");
>
> @@ -558,6 +559,17 @@ static void intel_dsi_pre_enable(struct
> intel_encoder *encoder,
> intel_disable_dsi_pll(encoder);
> intel_enable_dsi_pll(encoder, pipe_config);
>
> + if (IS_BROXTON(dev_priv)) {
> + /* Add MIPI IO reset programming for modeset */
> + val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
> + I915_WRITE(BXT_P_CR_GT_DISP_PWRON,
> + val | MIPIO_RST_CTRL);
> +
> + /* Power up DSI regulator */
> + I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
> + I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, 0);
> + }
> +
> intel_dsi_prepare(encoder, pipe_config);
>
> /* Panel Enable over CRC PMIC */
> @@ -707,6 +719,7 @@ static void intel_dsi_post_disable(struct
> intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder-
> >base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder-
> >base);
> + u32 val;
>
> DRM_DEBUG_KMS("\n");
>
> @@ -714,6 +727,17 @@ static void intel_dsi_post_disable(struct
> intel_encoder *encoder,
>
> intel_dsi_clear_device_ready(encoder);
>
> + if (IS_BROXTON(dev_priv)) {
> + /* Power down DSI regulator to save power */
> + I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
> + I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL,
> HS_IO_CTRL_SELECT);
> +
> + /* Add MIPI IO reset programming for modeset */
> + val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
> + I915_WRITE(BXT_P_CR_GT_DISP_PWRON,
> + val & ~MIPIO_RST_CTRL);
> + }
> +
> intel_disable_dsi_pll(encoder);
>
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
--
Mika Kahola - Intel OTC
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