Currently we use an empirically derived sleep for waiting fr the seqno to be coherent following an interrupt on Ironlake. However, that is occasionally too short and we get a missed-interrupt warning from CI. We can use the sync-flush dance now employed for gen6 for a more realistic delay, and hopefully kill 2 birds with one barrier.
Signed-off-by: Chris Wilson <[email protected]> --- drivers/gpu/drm/i915/intel_ringbuffer.c | 22 ++-------------------- 1 file changed, 2 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index d1f408938479..9673eaf05ec9 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1473,24 +1473,6 @@ gen6_ring_sync_to(struct drm_i915_gem_request *req, static void gen5_seqno_barrier(struct intel_engine_cs *engine) { - /* MI_STORE are internally buffered by the GPU and not flushed - * either by MI_FLUSH or SyncFlush or any other combination of - * MI commands. - * - * "Only the submission of the store operation is guaranteed. - * The write result will be complete (coherent) some time later - * (this is practically a finite period but there is no guaranteed - * latency)." - * - * Empirically, we observe that we need a delay of at least 75us to - * be sure that the seqno write is visible by the CPU. - */ - usleep_range(125, 250); -} - -static void -gen6_seqno_barrier(struct intel_engine_cs *engine) -{ struct drm_i915_private *dev_priv = engine->i915; i915_reg_t reg = RING_INSTPM(engine->mmio_base); @@ -2602,11 +2584,11 @@ static void intel_ring_init_irq(struct drm_i915_private *dev_priv, if (INTEL_GEN(dev_priv) >= 8) { engine->irq_enable = gen8_irq_enable; engine->irq_disable = gen8_irq_disable; - engine->irq_seqno_barrier = gen6_seqno_barrier; + engine->irq_seqno_barrier = gen5_seqno_barrier; } else if (INTEL_GEN(dev_priv) >= 6) { engine->irq_enable = gen6_irq_enable; engine->irq_disable = gen6_irq_disable; - engine->irq_seqno_barrier = gen6_seqno_barrier; + engine->irq_seqno_barrier = gen5_seqno_barrier; } else if (INTEL_GEN(dev_priv) >= 5) { engine->irq_enable = gen5_irq_enable; engine->irq_disable = gen5_irq_disable; -- 2.11.0 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
