On Tue, Feb 28, 2017 at 09:21:12AM +0200, Ander Conselvan de Oliveira wrote:
> Commit 62b695662a24 ("drm/i915: Only enable DDI IO power domains after
> enabling DPLL") changed how the DDI IO power domains get enabled, but
> neglected the need to enable those domains when enabling a DP connector
> with MST enabled, leading to
>
> Kernel panic - not syncing: Timeout: Not all CPUs entered broadcast
> exception handler
>
> Fixes: 62b695662a24 ("drm/i915: Only enable DDI IO power domains after
> enabling DPLL")
> Cc: David Weinehall <[email protected]>
> Cc: Imre Deak <[email protected]>
> Cc: Ander Conselvan de Oliveira <[email protected]>
> Cc: David Weinehall <[email protected]>
> Cc: Daniel Vetter <[email protected]>
> Cc: Jani Nikula <[email protected]>
> Cc: [email protected]
> Cc: Ville Syrjälä <[email protected]>
> Reported-by: Ville Syrjälä <[email protected]>
> Signed-off-by: Ander Conselvan de Oliveira
> <[email protected]>
Reviewed-by: Imre Deak <[email protected]>
> ---
> drivers/gpu/drm/i915/intel_dp_mst.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
> b/drivers/gpu/drm/i915/intel_dp_mst.c
> index d94fd4b..a8334e1 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -163,6 +163,9 @@ static void intel_mst_pre_enable_dp(struct intel_encoder
> *encoder,
> intel_ddi_clk_select(&intel_dig_port->base,
> pipe_config->shared_dpll);
>
> + intel_display_power_get(dev_priv,
> + intel_dig_port->ddi_io_power_domain);
> +
> intel_prepare_dp_ddi_buffers(&intel_dig_port->base);
> intel_dp_set_link_params(intel_dp,
> pipe_config->port_clock,
> --
> 2.9.3
>
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