From: Shobhit Kumar <shobhit.ku...@intel.com>
PIPE EDP registers and timing registers are different for EDP on HSW
Signed-off-by: Shobhit Kumar <shobhit.ku...@intel.com>
Signed-off-by: Sateesh Kavuri <sateesh.kav...@intel.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodo...@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0c53e4a..1e70fae 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1528,6 +1528,14 @@
#define _BCLRPAT_B 0x61020
#define _VSYNCSHIFT_B 0x61028
+/* Pipe EDP timing regs */
+#define HTOTAL_EDP 0x6F000
+#define HBLANK_EDP 0x6F004
+#define HSYNC_EDP 0x6F008
+#define VTOTAL_EDP 0x6F00C
+#define VBLANK_EDP 0x6F010
+#define VSYNC_EDP 0x6F014
+#define VSYNCSHIFT_EDP 0x6F028
#define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B)
#define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B)
@@ -3243,6 +3251,19 @@
#define _PIPEB_LINK_M2 0x61048
#define _PIPEB_LINK_N2 0x6104c
+/* PIPE EDP timing regs */
+#define PIPEEDP_DATA_M1 0x6F030
+#define PIPEEDP_DATA_N1 0x6F034
+
+#define PIPDEDP_DATA_M2 0x6F038
+#define PIPEEDP_DATA_N2 0x6F03C
+
+#define PIPEEDP_LINK_M1 0x6F040
+#define PIPEEDP_LINK_N1 0x6F044
+
+#define PIPEEDP_LINK_M2 0x6F048
+#define PIPEEDP_LINK_N2 0x6F04C
+
#define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
#define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
#define PIPE_DATA_M2(pipe) _PIPE(pipe, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
@@ -4277,6 +4298,12 @@
#define PIPE_DDI_FUNC_CTL_B 0x61400
#define PIPE_DDI_FUNC_CTL_C 0x62400
#define PIPE_DDI_FUNC_CTL_EDP 0x6F400
+#define PIPE_DDI_EDP_INPUT_SRC_MASK (7<<12)
+#define PIPE_DDI_EDI_INPUT_SRC_A_ON (0<<12)
+#define PIPE_DDI_EDI_INPUT_SRC_A_ON_OFF (4<<12)
+#define PIPE_DDI_EDI_INPUT_SRC_B_ON_OFF (5<<12)
+#define PIPE_DDI_EDI_INPUT_SRC_C_ON_OFF (6<<12)
+
#define DDI_FUNC_CTL(pipe) _PIPE(pipe, \
PIPE_DDI_FUNC_CTL_A, \
PIPE_DDI_FUNC_CTL_B)
@@ -4345,6 +4372,8 @@
#define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */
#define DDI_BUF_EMP_MASK (0xf<<24)
#define DDI_BUF_IS_IDLE (1<<7)
+#define DDI_PORT_LANE_CAP_DDIA_4 (1<<4)
+#define DDI_PORT_LANE_CAP_DDIA_2 (0<<4)
#define DDI_PORT_WIDTH_MASK (7<<1)
#define DDI_PORT_WIDTH_X1 (0<<1)
#define DDI_PORT_WIDTH_X2 (1<<1)
@@ -4463,6 +4492,8 @@
#define HSW_MSA_BPC_12_BITS (3<<5)
#define HSW_MSA_BPC_16_BITS (4<<5)
+#define HSW_MSA_EDP_CTL 0x6F410
+
/* Pipe WM_LINETIME - watermark line time */
#define PIPE_WM_LINETIME_A 0x45270
#define PIPE_WM_LINETIME_B 0x45274
--
1.7.11.1
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