> -----Original Message----- > From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] > Sent: Monday, August 7, 2017 7:13 PM > To: Dong, Chuanxiao <chuanxiao.d...@intel.com>; intel- > g...@lists.freedesktop.org; Joonas Lahtinen > <joonas.lahti...@linux.intel.com> > Subject: RE: a potential dead loop in intel_lrc_irq_handler > > Quoting Dong, Chuanxiao (2017-08-07 11:31:57) > > > -----Original Message----- > > > From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] GPU reset -> > > > clears CSB head/tail > > But the GPU reset will make CSB_head = 0 and CSB_tail = 7. > > Experience says otherwise, but the issue of the delayed interrupt is still a > concern. > > On the per-engine reset path, interrupts are not disabled, so once we disable > the tasklet and cancel the pending execution across the reset, we should be > fine. > > It's the full reset path, where we disable the interrupt first, we need to be > careful about the hw keeping the interrupt around. Certainly we have no > fundamental reason to disable_irq there, the supposition is that we are safer > without spurious interrupts we aren't ready to handle. But afaics to put your > mind at rest all we need is an > > I915_WRITE(GEN8_GT_IIR[engine->irq_idx], > GT_CONTEXT_SWITCH_INTERRUPT << engine->irq_shift); > I915_WRITE(GEN8_GT_IIR[engine->irq_idx], > GT_CONTEXT_SWITCH_INTERRUPT << engine->irq_shift); > > as we process the reset. > -Chris
Yes, if we cleared the pending context switch interrupt in IIR, it should be fine. Is there a patch which is trying to do so? Thanks Chuanxiao _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
