Quoting Daniel Vetter (2017-08-07 17:20:27)
> On Fri, Aug 04, 2017 at 11:23:18AM -0700, clinton.a.tay...@intel.com wrote:
> > From: Clint Taylor <clinton.a.tay...@intel.com>
> > 
> > Current 50ms max threshold timing for an EDID read is very close to the
> > actual time for a 2 block HDMI EDID read of 48ms. Any delay like a clock
> > stretch by the EDID eeprom will cause this test to fail. A 4 block HDMI
> > EDID read takes approximately 88ms under nominal conditions, making the max
> > threshold 95ms will allow this test to pass regardless of monitor attached.
> > 
> > Signed-off-by: Clint Taylor <clinton.a.tay...@intel.com>
> Per internal mail, this needs to be runtime adjusted to fit the EDID we're
> reading. Maybe 30ms per edid block.

Those are scary numbers. So please also a kms_flip flip-vs-edid
with timestamp check. Given the number of random probes we do, we must
make sure that we can do those in parallel to driving the display
fluidly. Similarly, some crc testing against edid reading would be in
order to make sure that there are no display glitches during the
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