On Wed, Oct 11, 2017 at 07:04:50PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä <[email protected]> > > Replace the 0 and 1 with PLANE_A and PLANE_B in the pre-g4x wm code. > > Signed-off-by: Ville Syrjälä <[email protected]>
With the bikeshed from the preceeding patch applied here too: Reviewed-by: Daniel Vetter <[email protected]> > --- > drivers/gpu/drm/i915/i915_drv.h | 3 ++- > drivers/gpu/drm/i915/intel_pm.c | 36 +++++++++++++++++++----------------- > 2 files changed, 21 insertions(+), 18 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 7280f9eb2e95..df120a38ae42 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -699,7 +699,8 @@ struct drm_i915_display_funcs { > struct intel_cdclk_state *cdclk_state); > void (*set_cdclk)(struct drm_i915_private *dev_priv, > const struct intel_cdclk_state *cdclk_state); > - int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane); > + int (*get_fifo_size)(struct drm_i915_private *dev_priv, > + enum old_plane_id plane_id); > int (*compute_pipe_wm)(struct intel_crtc_state *cstate); > int (*compute_intermediate_wm)(struct drm_device *dev, > struct intel_crtc *intel_crtc, > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 2fcff9788b6f..13f1010eea77 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -521,38 +521,41 @@ static void vlv_get_fifo_size(struct intel_crtc_state > *crtc_state) > fifo_state->plane[PLANE_CURSOR] = 63; > } > > -static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, int plane) > +static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, > + enum old_plane_id plane_id) > { > uint32_t dsparb = I915_READ(DSPARB); > int size; > > size = dsparb & 0x7f; > - if (plane) > + if (plane_id == PLANE_B) > size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; > > - DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, > - plane ? "B" : "A", size); > + DRM_DEBUG_KMS("FIFO size - (0x%08x) %c: %d\n", > + dsparb, plane_name(plane_id), size); > > return size; > } > > -static int i830_get_fifo_size(struct drm_i915_private *dev_priv, int plane) > +static int i830_get_fifo_size(struct drm_i915_private *dev_priv, > + enum old_plane_id plane_id) > { > uint32_t dsparb = I915_READ(DSPARB); > int size; > > size = dsparb & 0x1ff; > - if (plane) > + if (plane_id == PLANE_B) > size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; > size >>= 1; /* Convert to cachelines */ > > - DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, > - plane ? "B" : "A", size); > + DRM_DEBUG_KMS("FIFO size - (0x%08x) %c: %d\n", > + dsparb, plane_name(plane_id), size); > > return size; > } > > -static int i845_get_fifo_size(struct drm_i915_private *dev_priv, int plane) > +static int i845_get_fifo_size(struct drm_i915_private *dev_priv, > + enum old_plane_id plane_id) > { > uint32_t dsparb = I915_READ(DSPARB); > int size; > @@ -560,9 +563,8 @@ static int i845_get_fifo_size(struct drm_i915_private > *dev_priv, int plane) > size = dsparb & 0x7f; > size >>= 2; /* Convert to cachelines */ > > - DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, > - plane ? "B" : "A", > - size); > + DRM_DEBUG_KMS("FIFO size - (0x%08x) %c: %d\n", > + dsparb, plane_name(plane_id), size); > > return size; > } > @@ -2261,8 +2263,8 @@ static void i9xx_update_wm(struct intel_crtc > *unused_crtc) > else > wm_info = &i830_a_wm_info; > > - fifo_size = dev_priv->display.get_fifo_size(dev_priv, 0); > - crtc = intel_get_crtc_for_plane(dev_priv, 0); > + fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_A); > + crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A); > if (intel_crtc_active(crtc)) { > const struct drm_display_mode *adjusted_mode = > &crtc->config->base.adjusted_mode; > @@ -2288,8 +2290,8 @@ static void i9xx_update_wm(struct intel_crtc > *unused_crtc) > if (IS_GEN2(dev_priv)) > wm_info = &i830_bc_wm_info; > > - fifo_size = dev_priv->display.get_fifo_size(dev_priv, 1); > - crtc = intel_get_crtc_for_plane(dev_priv, 1); > + fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B); > + crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B); > if (intel_crtc_active(crtc)) { > const struct drm_display_mode *adjusted_mode = > &crtc->config->base.adjusted_mode; > @@ -2401,7 +2403,7 @@ static void i845_update_wm(struct intel_crtc > *unused_crtc) > adjusted_mode = &crtc->config->base.adjusted_mode; > planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, > &i845_wm_info, > - > dev_priv->display.get_fifo_size(dev_priv, 0), > + > dev_priv->display.get_fifo_size(dev_priv, PLANE_A), > 4, pessimal_latency_ns); > fwater_lo = I915_READ(FW_BLC) & ~0xfff; > fwater_lo |= (3<<8) | planea_wm; > -- > 2.13.6 > > _______________________________________________ > Intel-gfx mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
