Quoting Michel Thierry (2018-01-10 19:04:45)
> On 1/10/2018 10:18 AM, Chris Wilson wrote:
> > Quoting Oscar Mateo (2017-12-22 22:38:49)
> >> This register does not contain it. Instead, we have to look into
> >> FAULT_TLB_DATA0 & 1
> >> (where, by the way, we can also get the address space).
> >>
> >> v2: Right formatting
> >> v3:
> >> - Use 12 (as per the register format) instead of PAGE_SIZE (Chris)
> >> - s/BITS_44_TO_47/HIGHBITS (Chris)
> >> - Right formatting, this time for real
> >>
> >> Fixes: b03ec3d67ab8 ("drm/i915: There is only one fault register from GEN8
> >> onwards")
> >> Signed-off-by: Oscar Mateo <[email protected]>
> >> Cc: Michel Thierry <[email protected]>
> >> Cc: Chris Wilson <[email protected]>
> >
> > Michel, can you double check the regs?
>
> Sorry, forgot about this.
>
> > -Chris
> >
> >> ---
> >> drivers/gpu/drm/i915/i915_gem_gtt.c | 15 +++++++++++++--
> >> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> >> 2 files changed, 15 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> >> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> >> index c5f3938..0de4f3f 100644
> >> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> >> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> >> @@ -2287,12 +2287,23 @@ static void gen8_check_and_clear_faults(struct
> >> drm_i915_private *dev_priv)
> >> u32 fault = I915_READ(GEN8_RING_FAULT_REG);
> >>
> >> if (fault & RING_FAULT_VALID) {
> >> + u32 fault_data0, fault_data1;
> >> + u64 fault_addr;
> >> +
> >> + fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
> >> + fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
> >> + fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) <<
> >> 44) |
> >> + ((u64)fault_data0 << 12);
> >> +
> >> DRM_DEBUG_DRIVER("Unexpected fault\n"
> >> - " Addr: 0x%08lx\n"
> >> + " Addr: 0x%08x_%08x\n"
> >> + " Address space: %s\n"
> >> " Engine ID: %d\n"
> >> " Source ID: %d\n"
> >> " Type: %d\n",
> >> - fault & PAGE_MASK,
> >> + upper_32_bits(fault_addr),
> >> + lower_32_bits(fault_addr),
> >> + fault_data1 & FAULT_GTT_SEL ? "GGTT" :
> >> "PPGTT",
> >> GEN8_RING_FAULT_ENGINE_ID(fault),
> >> RING_FAULT_SRCID(fault),
> >> RING_FAULT_FAULT_TYPE(fault));
> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> >> b/drivers/gpu/drm/i915/i915_reg.h
> >> index 41285be..a499618 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -2489,6 +2489,8 @@ enum i915_power_well_id {
> >>
> >> #define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10)
> >> #define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14)
> >> +#define FAULT_VA_HIGH_BITS (0xf << 0)
> >> +#define FAULT_GTT_SEL (1 << 4)
> >>
>
> Matches what the spec says, IHD-OS-SKL-Vol 2c-05.16 pages 617-618 [1]
> (which is not different from the BDW and CHV/BSW ones).
>
> Reviewed-by: Michel Thierry <[email protected]>
Many thanks, for both the patch and review, pushed.
-Chris
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