We already do that as part of the ringbuffer re-setup at resume time. Furthermore the register offset has moved on gen6+ around quite a bit, and on ilk/gm45 we also need to restore the HWS reg for the bsd ring, not just the render ring.
So again in kms mode this is only confusing a best, hence don't bother. v2: Fixup logic, noticed by Paulo Zanoni. Signed-off-by: Daniel Vetter <[email protected]> --- drivers/gpu/drm/i915/i915_suspend.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index ac6d412..33121aa 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c @@ -814,7 +814,8 @@ int i915_save_state(struct drm_device *dev) mutex_lock(&dev->struct_mutex); /* Hardware status page */ - dev_priv->saveHWS = I915_READ(HWS_PGA); + if (!drm_core_check_feature(dev, DRIVER_MODESET)) + dev_priv->saveHWS = I915_READ(HWS_PGA); i915_save_display(dev); @@ -867,7 +868,8 @@ int i915_restore_state(struct drm_device *dev) mutex_lock(&dev->struct_mutex); /* Hardware status page */ - I915_WRITE(HWS_PGA, dev_priv->saveHWS); + if (!drm_core_check_feature(dev, DRIVER_MODESET)) + I915_WRITE(HWS_PGA, dev_priv->saveHWS); i915_restore_display(dev); -- 1.7.11.7 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
