Since intel_sideband_read and intel_sideband_write differ by only a
couple of lines (depending on whether we feed the value in or out),
merge the two into a single common accessor.

Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/intel_sideband.c | 93 +++++++++++++----------------------
 1 file changed, 33 insertions(+), 60 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_sideband.c 
b/drivers/gpu/drm/i915/intel_sideband.c
index 87e34787939b..e5faebb511ae 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -309,91 +309,64 @@ void vlv_dpio_put(struct drm_i915_private *dev_priv)
 }
 
 /* SBI access */
-u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
-                  enum intel_sbi_destination destination)
+static int intel_sbi_rw(struct drm_i915_private *dev_priv, u16 reg,
+                       enum intel_sbi_destination destination,
+                       u32 *val, bool is_read)
 {
-       u32 value = 0;
+       u32 cmd;
 
        lockdep_assert_held(&dev_priv->sb_lock);
 
-       if (intel_wait_for_register(dev_priv,
-                                   SBI_CTL_STAT, SBI_BUSY, 0,
-                                   100)) {
+       if (intel_wait_for_register_fw(dev_priv,
+                                      SBI_CTL_STAT, SBI_BUSY, 0,
+                                      100)) {
                DRM_ERROR("timeout waiting for SBI to become ready\n");
-               return 0;
+               return -EBUSY;
        }
 
-       I915_WRITE(SBI_ADDR, (reg << 16));
-       I915_WRITE(SBI_DATA, 0);
+       I915_WRITE_FW(SBI_ADDR, (u32)reg << 16);
+       I915_WRITE_FW(SBI_DATA, is_read ? 0 : *val);
 
        if (destination == SBI_ICLK)
-               value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
+               cmd = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
        else
-               value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
-       I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
+               cmd = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
+       if (!is_read)
+               cmd |= BIT(8);
+       I915_WRITE_FW(SBI_CTL_STAT, cmd | SBI_BUSY);
 
-       if (intel_wait_for_register(dev_priv,
-                                   SBI_CTL_STAT,
-                                   SBI_BUSY,
-                                   0,
-                                   100)) {
+       if (__intel_wait_for_register_fw(dev_priv,
+                                        SBI_CTL_STAT, SBI_BUSY, 0,
+                                        100, 100, &cmd)) {
                DRM_ERROR("timeout waiting for SBI to complete read\n");
-               return 0;
+               return -ETIMEDOUT;
        }
 
-       if (I915_READ(SBI_CTL_STAT) & SBI_RESPONSE_FAIL) {
+       if (cmd & SBI_RESPONSE_FAIL) {
                DRM_ERROR("error during SBI read of reg %x\n", reg);
-               return 0;
+               return -ENXIO;
        }
 
-       return I915_READ(SBI_DATA);
+       if (is_read)
+               *val = I915_READ_FW(SBI_DATA);
+
+       return 0;
 }
 
-void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
-                    enum intel_sbi_destination destination)
+u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
+                  enum intel_sbi_destination destination)
 {
-       u32 tmp;
-
-       lockdep_assert_held(&dev_priv->sb_lock);
-
-       if (intel_wait_for_register(dev_priv,
-                                   SBI_CTL_STAT, SBI_BUSY, 0,
-                                   100)) {
-               DRM_ERROR("timeout waiting for SBI to become ready\n");
-               return;
-       }
+       u32 result = 0;
 
-       I915_WRITE(SBI_ADDR, (reg << 16));
-       I915_WRITE(SBI_DATA, value);
-
-       if (destination == SBI_ICLK)
-               tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
-       else
-               tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
-       I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
-
-       if (intel_wait_for_register(dev_priv,
-                                   SBI_CTL_STAT,
-                                   SBI_BUSY,
-                                   0,
-                                   100)) {
-               DRM_ERROR("timeout waiting for SBI to complete write\n");
-               return;
-       }
+       intel_sbi_rw(dev_priv, reg, destination, &result, true);
 
-       if (I915_READ(SBI_CTL_STAT) & SBI_RESPONSE_FAIL) {
-               DRM_ERROR("error during SBI write of %x to reg %x\n",
-                         value, reg);
-               return;
-       }
+       return result;
 }
 
-u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg)
+void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
+                    enum intel_sbi_destination destination)
 {
-       u32 val = 0;
-       vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,
-                       reg, &val);
-       return val;
+       intel_sbi_rw(dev_priv, reg, destination, &value, false);
 }
 
 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
-- 
2.16.2

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