On Thu, Mar 22, 2018 at 02:48:44PM -0700, José Roberto de Souza wrote:
> This value do not change overtime so better cache it than
> fetch it every PSR enable.
>
> Signed-off-by: José Roberto de Souza <[email protected]>
> Cc: Dhinakaran Pandiyan <[email protected]>
> Cc: Rodrigo Vivi <[email protected]>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_psr.c | 28 ++++++++++++++++------------
> 2 files changed, 17 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index a367fe5538ae..f79338821081 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -607,6 +607,7 @@ struct i915_psr {
> bool alpm;
> bool has_hw_tracking;
> bool psr2_enabled;
> + u8 sink_sync_latency;
>
> void (*enable_source)(struct intel_dp *,
> const struct intel_crtc_state *);
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index ad69722c329d..19ee6120d3cd 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -122,6 +122,18 @@ static bool intel_dp_get_alpm_status(struct intel_dp
> *intel_dp)
> return alpm_caps & DP_ALPM_CAP;
> }
>
> +static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
> +{
> + u8 val = 0;
> +
> + if (drm_dp_dpcd_readb(&intel_dp->aux,
> + DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1)
> + val &= DP_MAX_RESYNC_FRAME_COUNT_MASK;
> + else
> + DRM_ERROR("Unable to get sink synchronization latency\n");
> + return val;
> +}
> +
> void intel_psr_init_dpcd(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv =
> @@ -158,6 +170,8 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
> intel_dp_get_colorimetry_status(intel_dp);
> dev_priv->psr.alpm =
> intel_dp_get_alpm_status(intel_dp);
> + dev_priv->psr.sink_sync_latency =
> + intel_dp_get_sink_sync_latency(intel_dp);
> }
> }
> }
> @@ -380,10 +394,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> * with the 5 or 6 idle patterns.
> */
> uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> - uint32_t val;
> - uint8_t sink_latency;
> -
> - val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
> + u32 val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT;
This belongs to the previous patch apparently. With this moved there keep my
rv-b there
and add my rv-b here...
>
> /* FIXME: selective update is probably totally broken because it doesn't
> * mesh at all with our frontbuffer tracking. And the hw alone isn't
> @@ -393,14 +404,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> val |= EDP_Y_COORDINATE_VALID | EDP_Y_COORDINATE_ENABLE;
> }
>
> - if (drm_dp_dpcd_readb(&intel_dp->aux,
> - DP_SYNCHRONIZATION_LATENCY_IN_SINK,
> - &sink_latency) == 1) {
> - sink_latency &= DP_MAX_RESYNC_FRAME_COUNT_MASK;
> - } else {
> - sink_latency = 0;
> - }
> - val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency + 1);
> + val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
>
> if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> val |= EDP_PSR2_TP2_TIME_2500;
> --
> 2.16.2
>
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