On Fri, 26 Oct 2012 09:42:42 -0700, Jesse Barnes <[email protected]> wrote: > commit b99c792eddf804150b3341a85c256df50d7ab5c2 > Author: Jesse Barnes <[email protected]> > Date: Wed Sep 19 13:02:39 2012 -0700 > > drm/i915: TLB invalidation with MI_FLUSH_DW requires a post-sync op v3 > > So store into the scratch space of the HWS to make sure the invalidate > occurs. > > v2: use GTT address space for store, clean up #defines (Chris) > v3: use correct #define in blt ring flush (Chris) > > Signed-off-by: Jesse Barnes <[email protected]>
Reviewed-by: Chris Wilson <[email protected]> That looks to be the code I executed, but I can't confirm it fixes any problems. References: https://bugs.launchpad.net/ubuntu/+source/xserver-xorg-video-intel/+bug/1063252 which looks to be a likely victim of a missing TLB flush on the blitter ring. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
