Mostly paranoia as the writes to the ring registers should not be reordered, but it should function well as an addition explicit check in a mysteriously fragile bit of code.
References: https://bugs.freedesktop.org/show_bug.cgi?id=54575 Signed-off-by: Chris Wilson <[email protected]> --- drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 53edce0..d5d5177 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -393,6 +393,9 @@ static int init_ring_common(struct intel_ring_buffer *ring) * also enforces ordering), otherwise the hw might lose the new ring * register values. */ I915_WRITE_START(ring, obj->gtt_offset); + if (I915_READ_START(ring) != obj->gtt_offset) + DRM_ERROR("failed to set %s start to GTT offset\n", ring->name); + I915_WRITE_CTL(ring, ((ring->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID); -- 1.7.10.4 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
