Quoting Mahesh Kumar (2018-08-01 16:11:13)
> We distribute DDB equally among all pipes irrespective of display
> buffer requirement of each pipe. This leads to a situation where high
> resolution y-tiled display can not be enabled with 2 low resolution
> displays.
>
> Main contributing factor for DDB requirement is width of the display.
> This patch make changes to distribute ddb based on display width.
> So display with higher width will get bigger chunk of DDB.
>
> Changes Since V1:
> - pipe_size/ddb_size will not overflow u16 so use appropriate
> data-types during computation (Chris)
> Changes Since V2:
> - avoid redundancy and possible truncation errors (Chris)
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107113
> Cc: [email protected]
> Cc: Chris Wilson <[email protected]>
> Signed-off-by: Mahesh Kumar <[email protected]>
Reviewed-by: Chris Wilson <[email protected]>
-Chris
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
