Quoting Lionel Landwerlin (2018-10-10 17:55:33) > @@ -1518,12 +1520,14 @@ static int alloc_oa_buffer(struct drm_i915_private > *dev_priv) > goto err_unref; > > /* PreHSW required 512K alignment, HSW requires 16M */ > - vma = i915_gem_object_ggtt_pin(bo, NULL, 0, SZ_16M, 0); > + vma = i915_gem_object_ggtt_pin(bo, NULL, 0, size, 0);
That's not size, that's align. Presumably this doesn't change as HSW is still going to require 16MiB? -Chris _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
