On Tue, Oct 16, 2018 at 03:01:32PM -0700, Paulo Zanoni wrote: > With this one here we can finally drop the intel state structures from > the functions that compute watermark values: they all rely on struct > skl_wm_params now. This should help the watermarks code be a little > more clear on its intent and also match the spec a little bit more > with the carefully chosen names for its parameters.
I guess we'll just roll with the duplication. Reviewed-by: Ville Syrjälä <[email protected]> > > Signed-off-by: Paulo Zanoni <[email protected]> > --- > drivers/gpu/drm/i915/i915_drv.h | 1 + > drivers/gpu/drm/i915/intel_pm.c | 20 ++++++++------------ > 2 files changed, 9 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index b32d680d9bf0..4712eaea9744 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1254,6 +1254,7 @@ struct skl_wm_params { > bool x_tiled, y_tiled; > bool rc_surface; > bool is_planar; > + uint32_t pipe_htotal; > uint32_t width; > uint16_t ddb_blocks; > uint8_t cpp; > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index d101c542f10d..b01f3d807ff6 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4549,6 +4549,8 @@ skl_compute_plane_wm_params(const struct > drm_i915_private *dev_priv, > fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS; > wp->is_planar = fb->format->format == DRM_FORMAT_NV12; > > + wp->pipe_htotal = cstate->base.adjusted_mode.crtc_htotal; > + > if (plane->id == PLANE_CURSOR) { > wp->width = intel_pstate->base.crtc_w; > } else { > @@ -4630,7 +4632,6 @@ skl_compute_plane_wm_params(const struct > drm_i915_private *dev_priv, > } > > static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, > - struct intel_crtc_state *cstate, > int level, > const struct skl_wm_params *wp, > const struct skl_wm_level *result_prev, > @@ -4659,17 +4660,15 @@ static int skl_compute_plane_wm(const struct > drm_i915_private *dev_priv, > > method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate, > wp->cpp, latency, wp->dbuf_block_size); > - method2 = skl_wm_method2(wp->plane_pixel_rate, > - cstate->base.adjusted_mode.crtc_htotal, > + method2 = skl_wm_method2(wp->plane_pixel_rate, wp->pipe_htotal, > latency, > wp->plane_blocks_per_line); > > if (wp->y_tiled) { > selected_result = max_fixed16(method2, wp->y_tile_minimum); > } else { > - if ((wp->cpp * cstate->base.adjusted_mode.crtc_htotal / > - wp->dbuf_block_size < 1) && > - (wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) { > + if ((wp->cpp * wp->pipe_htotal / wp->dbuf_block_size < 1) && > + (wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) { > selected_result = method2; > } else if (wp->ddb_blocks >= > fixed16_to_u32_round_up(wp->plane_blocks_per_line)) { > @@ -4782,7 +4781,6 @@ static int skl_compute_plane_wm(const struct > drm_i915_private *dev_priv, > > static int > skl_compute_wm_levels(const struct drm_i915_private *dev_priv, > - struct intel_crtc_state *cstate, > const struct skl_wm_params *wm_params, > struct skl_plane_wm *wm, > int plane_id) > @@ -4802,7 +4800,6 @@ skl_compute_wm_levels(const struct drm_i915_private > *dev_priv, > result_prev = plane_id ? &wm->uv_wm[0] : &wm->wm[0]; > > ret = skl_compute_plane_wm(dev_priv, > - cstate, > level, > wm_params, > result_prev, > @@ -4937,8 +4934,7 @@ static int skl_build_pipe_wm(struct intel_crtc_state > *cstate, > if (!wm_params.plane_visible) > continue; > > - ret = skl_compute_wm_levels(dev_priv, cstate, &wm_params, wm, > - 0); > + ret = skl_compute_wm_levels(dev_priv, &wm_params, wm, 0); > if (ret) { > DRM_DEBUG_KMS("[PLANE:%d:%s] failed to compute > watermark levels\n", > plane->base.id, plane->name); > @@ -4956,8 +4952,8 @@ static int skl_build_pipe_wm(struct intel_crtc_state > *cstate, > if (ret) > return ret; > > - ret = skl_compute_wm_levels(dev_priv, cstate, > - &wm_params, wm, 1); > + ret = skl_compute_wm_levels(dev_priv, &wm_params, wm, > + 1); > if (ret) { > DRM_DEBUG_KMS("[PLANE:%d:%s] failed to compute > planar watermark levels\n", > plane->base.id, plane->name); > -- > 2.14.4 > > _______________________________________________ > Intel-gfx mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
