Quoting Daniele Ceraolo Spurio (2019-03-21 22:02:06) > The upcoming unified GuC FW will require us to send video engine enable > masks to GuC for its initialization. > > For consistency, just set the runtime_info enable masks for all gens. > We'll then be able to directly use those in the GuC setup > > Cc: Michal Wajdeczko <[email protected]> > Cc: John Spotswood <[email protected]> > Cc: Eric Betancourt <[email protected]> > Signed-off-by: Daniele Ceraolo Spurio <[email protected]> > --- > drivers/gpu/drm/i915/intel_device_info.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c > b/drivers/gpu/drm/i915/intel_device_info.c > index eddf83807957..836184d6538e 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -872,8 +872,14 @@ void intel_device_info_init_mmio(struct drm_i915_private > *dev_priv) > unsigned int i; > u32 media_fuse; > > - if (INTEL_GEN(dev_priv) < 11) > + if (INTEL_GEN(dev_priv) < 11) { > + RUNTIME_INFO(dev_priv)->vdbox_enable = > + (info->engine_mask & GENMASK(VCS0 + I915_MAX_VCS, > VCS0)) >> VCS0; > + > + RUNTIME_INFO(dev_priv)->vebox_enable = > + (info->engine_mask & GENMASK(VECS0 + I915_MAX_VECS, > VECS0)) >> VECS0;
Should we do this unconditionally as it seems reasonably self-desciptive, with a follow to say that on gen11+ we can query the hw fuses to see what is actually available? -Chris _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
