Quoting José Roberto de Souza (2019-03-26 23:02:23)
> GT VEBOX DISABLE is only 4 bits wide but it was using a 8 bits wide
> mask, the remaning reserved bits is set to 0 causing 4 more
> nonexistent VEBOX engines being detected as enabled, triggering the
> BUG_ON() because of mismatch between vebox_mask and newly added
> VEBOX_MASK().
>
> [ 64.081621] [drm:intel_device_info_init_mmio [i915]] vdbox enable: 0005,
> instances: 0005
> [ 64.081763] [drm:intel_device_info_init_mmio [i915]] vebox enable: 00f1,
> instances: 0001
> [ 64.081825] intel_device_info_init_mmio:925 GEM_BUG_ON(vebox_mask != ({
> unsigned int first__ = (VECS0); unsigned int count__ = (2);
> ((&(dev_priv)->__info)->engine_mask & (((~0UL) - (1UL << (first__)) + 1) &
> (~0UL >> (64 - 1 - (first__ + count__ - 1))))) >> first__; }))
> [ 64.082047] ------------[ cut here ]------------
> [ 64.082054] kernel BUG at drivers/gpu/drm/i915/intel_device_info.c:925!
>
> BSpec: 20680
> Fixes: 9511cb6481af ("drm/i915: Adding missing '; ' to ENGINE_INSTANCES")
> Fixes: 26376a7e74d2 ("drm/i915/icl: Check for fused-off VDBOX and VEBOX
> instances")
Shooting the messenger, the fixes would be the incorrect
VEBOX_DISABLE_MASK would it not?
-Chris
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