If cat error is set, we need to clear it by acking it. Further, if it is set, we must not do a normal request for reset.
v2: avoid goto (Chris) Bspec: 12567 Cc: Chris Wilson <[email protected]> Signed-off-by: Mika Kuoppala <[email protected]> --- drivers/gpu/drm/i915/i915_reg.h | 6 ++++-- drivers/gpu/drm/i915/i915_reset.c | 32 ++++++++++++++++++------------- 2 files changed, 23 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8ad2f0a03f28..c1c0f7ab03e9 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2446,8 +2446,10 @@ enum i915_power_well_id { #define RING_HWS_PGA(base) _MMIO((base) + 0x80) #define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080) #define RING_RESET_CTL(base) _MMIO((base) + 0xd0) -#define RESET_CTL_REQUEST_RESET (1 << 0) -#define RESET_CTL_READY_TO_RESET (1 << 1) +#define RESET_CTL_CAT_ERROR REG_BIT(2) +#define RESET_CTL_READY_TO_RESET REG_BIT(1) +#define RESET_CTL_REQUEST_RESET REG_BIT(0) + #define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c) #define HSW_GTT_CACHE_EN _MMIO(0x4024) diff --git a/drivers/gpu/drm/i915/i915_reset.c b/drivers/gpu/drm/i915/i915_reset.c index d874a62103e5..75d66c47db48 100644 --- a/drivers/gpu/drm/i915/i915_reset.c +++ b/drivers/gpu/drm/i915/i915_reset.c @@ -491,25 +491,31 @@ static int gen8_engine_reset_prepare(struct intel_engine_cs *engine) { struct intel_uncore *uncore = engine->uncore; const i915_reg_t reg = RING_RESET_CTL(engine->mmio_base); - u32 ctl; + u32 ctl, ack = 0, mask = 0, request = 0; int ret; ctl = intel_uncore_read_fw(uncore, reg); - if (ctl & RESET_CTL_READY_TO_RESET) + + if (ctl & RESET_CTL_CAT_ERROR) { + request |= RESET_CTL_CAT_ERROR; + mask |= RESET_CTL_CAT_ERROR; + /* HAS#396813: Avoid reset request if cat error */ + } else if (!(ctl & RESET_CTL_READY_TO_RESET)) { + request |= RESET_CTL_REQUEST_RESET; + mask |= RESET_CTL_READY_TO_RESET; + ack |= RESET_CTL_READY_TO_RESET; + } else { return 0; + } - intel_uncore_write_fw(uncore, - reg, - _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET)); - - ret = __intel_wait_for_register_fw(uncore, - reg, - RESET_CTL_READY_TO_RESET, - RESET_CTL_READY_TO_RESET, - 700, 0, - NULL); + intel_uncore_write_fw(uncore, reg, _MASKED_BIT_ENABLE(request)); + + ret = __intel_wait_for_register_fw(uncore, reg, mask, ack, + 700, 0, NULL); if (ret) - DRM_ERROR("%s: reset request timeout\n", engine->name); + DRM_ERROR("%s: reset request 0x%08x timeout 0x%08x\n", + engine->name, request, + intel_uncore_read_fw(uncore, reg)); return ret; } -- 2.17.1 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
