Quoting Matt Roper (2019-08-15 22:58:59) > From the bspec: > > "SW must always program the FBC_RT_BASE_ADDR_REGISTER_* register > in Render Engine to a reserved value (0xFFFF_FFFF) such that the > programmed value doesn’t match the render target surface address > programmed. This would disable render engine from generating > modify messages to FBC unit in display." > > Bspec: 11388 > Bspec: 33451 > Cc: José Roberto de Souza <jose.so...@intel.com> > Signed-off-by: Matt Roper <matthew.d.ro...@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++ > drivers/gpu/drm/i915/i915_reg.h | 1 + > 2 files changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 704ace01e7f5..29b50e2c0627 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -567,6 +567,12 @@ static void icl_ctx_workarounds_init(struct > intel_engine_cs *engine, > /* allow headerless messages for preemptible GPGPU context */ > WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE, > GEN11_SAMPLER_ENABLE_HEADLESS_MSG); > + > + /* Wa_1604278689:icl,ehl */ > + wa_write_masked_or(wal, IVB_FBC_RT_BASE_UPPER, > + 0, /* write-only register; skip validation */ > + 0xFFFFFFFF); > + wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF);
It's part of the context? -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
