On Thu, 26 Sep 2019, Anna Karas <[email protected]> wrote:
> Replace PLLs names used in documentation to that used in the code.
>
> Cc: Vandita Kulkarni <[email protected]>
> Fixes: commit d0570414f3d1 ("drm/i915/tgl: Add new pll ids")
> Signed-off-by: Anna Karas <[email protected]>
If the previous version of your patch received Reviewed-by's, and your
patch does not change substantially, please include the Reviewed-by tags
in the new versions. (No need to repost just to add those.)
BR,
Jani.
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index e7588799fce5..104cf6d42333 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -147,11 +147,11 @@ enum intel_dpll_id {
> */
> DPLL_ID_ICL_MGPLL4 = 6,
> /**
> - * @DPLL_ID_TGL_TCPLL5: TGL TC PLL port 5 (TC5)
> + * @DPLL_ID_TGL_MGPLL5: TGL TC PLL port 5 (TC5)
> */
> DPLL_ID_TGL_MGPLL5 = 7,
> /**
> - * @DPLL_ID_TGL_TCPLL6: TGL TC PLL port 6 (TC6)
> + * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6)
> */
> DPLL_ID_TGL_MGPLL6 = 8,
> };
--
Jani Nikula, Intel Open Source Graphics Center
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