Quoting Mika Kuoppala (2019-10-11 14:39:10) > Add hdc pipeline flush to ensure memory state is coherent > in L3 when we are done. > > Signed-off-by: Mika Kuoppala <mika.kuopp...@linux.intel.com> > --- > drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 + > drivers/gpu/drm/i915/gt/intel_lrc.c | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h > b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h > index 8c8e6bf824a9..696b6495b0da 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h > +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h > @@ -232,6 +232,7 @@ > #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* > GM45+ only */ > #define PIPE_CONTROL_L3_RO_CACHE_INVALIDATE (1<<10) /* gen12 */ > #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) > +#define PIPE_CONTROL_HDC_PIPELINE_FLUSH (1<<9) /* gen 12 */
Ack. Just need to tweak usage. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
