On Tue, 25 Jun 2013 14:16:34 +0300 [email protected] wrote: > From: Ville Syrjälä <[email protected]> > > The PIPECONF color range bit doesn't appear to be effective, on HDMI > outputs at least. The color range bit in the port register works though, > so let's use it. > > I have not yet verified whether the PIPECONF bit works on DP outputs. > > This reverts commit 83a2af88f80ebf8104c9e083b786668b00f5b9ce. > > Signed-off-by: Ville Syrjälä <[email protected]> > --- > drivers/gpu/drm/i915/intel_hdmi.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c > b/drivers/gpu/drm/i915/intel_hdmi.c > index bc12518..98df2a0 100644 > --- a/drivers/gpu/drm/i915/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/intel_hdmi.c > @@ -602,7 +602,7 @@ static void intel_hdmi_mode_set(struct drm_encoder > *encoder, > u32 hdmi_val; > > hdmi_val = SDVO_ENCODING_HDMI; > - if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) > + if (!HAS_PCH_SPLIT(dev)) > hdmi_val |= intel_hdmi->color_range; > if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) > hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
Reviewed-by: Jesse Barnes <[email protected]> -- Jesse Barnes, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
