On Thu, 2020-03-12 at 15:08 -0700, José Roberto de Souza wrote:
> On Wed, 2020-03-11 at 09:22 -0700, Matt Roper wrote:
> > v2:
> > - Move to context workarounds. ROW_CHICKEN4 is part of the
> > context
> > image on gen11 (although it isn't on gen12).
> >
> > Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > 2 files changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 3bbd89294279..2318b55b9722 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -581,6 +581,9 @@ static void icl_ctx_workarounds_init(struct
> > intel_engine_cs *engine,
> > wa_write_masked_or(wal, IVB_FBC_RT_BASE_UPPER,
> > 0, /* write-only register; skip validation
> > */
> > 0xFFFFFFFF);
> > +
> > + /* Wa_1406306137:icl,ehl */
> > + wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU);
>
> The pre-gen12 definition of this registers don't have a masked access
> at least here on this on BSpec 11492
My bad, it just don't have it in the header.
Reviewed-by: José Roberto de Souza <jose.so...@intel.com>
>
> > }
> >
> > static void tgl_ctx_workarounds_init(struct intel_engine_cs
> > *engine,
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 92ae96cf5b64..b6941da3b588 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -9151,6 +9151,7 @@ enum {
> >
> > #define GEN9_ROW_CHICKEN4 _MMIO(0xe48c)
> > #define GEN12_DISABLE_TDL_PUSH REG_BIT(9)
> > +#define GEN11_DIS_PICK_2ND_EU REG_BIT(7)
> >
> > #define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
> > #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
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