As we initialize our own gamma LUT to sane values during initialisation, we should also update the user visible gamma ramp to match our settings. And before touching the storage for the user visible gamma ramp, we also need to check for an allocation failure.
v2: set_gamma_size() returns an error code, not success/fail. Also expand the 8bit LUT value to 16bit using bit replication. v3: Just log the error and disable gamma user functionality if we fail to allocate the ramp during initialisation. v4: Use pipe_name() and split the log message over multiple lines (vsyrjala) Signed-off-by: Chris Wilson <[email protected]> Cc: [email protected] Reviewed-by: Ville Syrjälä <[email protected]> --- drivers/gpu/drm/i915/intel_display.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 51730ce..6c9345e 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -8970,11 +8970,21 @@ static void intel_crtc_init(struct drm_device *dev, int pipe) drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); - drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); + if (drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256)) + DRM_ERROR("failed to allocate ramp for gamma" + " (will now be fixed at 1.0), on CRTC:%d (pipe %c)\n", + intel_crtc->base.base.id, + pipe_name(pipe)); + for (i = 0; i < 256; i++) { intel_crtc->lut_r[i] = i; intel_crtc->lut_g[i] = i; intel_crtc->lut_b[i] = i; + if (intel_crtc->base.gamma_size) { + intel_crtc->base.gamma_store[i + 0*256] = i << 8 | i; + intel_crtc->base.gamma_store[i + 1*256] = i << 8 | i; + intel_crtc->base.gamma_store[i + 2*256] = i << 8 | i; + } } /* Swap pipes & planes for FBC on pre-965 */ -- 1.8.3.1 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
