Quoting Mika Kuoppala (2020-04-14 13:20:00) > Hardware needs cacheline count for indirect context size. > Count of zero means that the feature is disabled. > If we only divide size with cacheline bytes, we get > one cacheline short of execution.
I thought we only emitted cacheline chunks by design? I see us checking for GEM_DEBUG_WARN_ON(!IS_ALIGNED(wa_bb[i]->offset, CACHELINE_BYTES))) so what's the reason? I expect that's in the next patch. -Chris _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
