On Wed, Feb 16, 2022 at 07:42:46PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä <[email protected]> > > If the only thing that is changing is SAGV vs. no SAGV but > the number of active planes and the total data rates end up > unchanged we currently bail out of intel_bw_atomic_check() > early and forget to actually compute the new WGV point > mask and thus won't actually enable/disable SAGV as requested. > This ends up poorly if we end up running with SAGV enabled > when we shouldn't. Usually ends up in underruns. > To fix this let's go through the QGV point mask computation > if anyone else already added the bw state for us. > > Cc: [email protected] > Cc: Stanislav Lisovskiy <[email protected]> > Fixes: 20f505f22531 ("drm/i915: Restrict qgv points which don't have enough > bandwidth.") > Signed-off-by: Ville Syrjälä <[email protected]>
Reviewed-by: Stanislav Lisovskiy <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_bw.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c > b/drivers/gpu/drm/i915/display/intel_bw.c > index 23aa8e06de18..d72ccee7d53b 100644 > --- a/drivers/gpu/drm/i915/display/intel_bw.c > +++ b/drivers/gpu/drm/i915/display/intel_bw.c > @@ -846,6 +846,13 @@ int intel_bw_atomic_check(struct intel_atomic_state > *state) > if (num_psf_gv_points > 0) > mask |= REG_GENMASK(num_psf_gv_points - 1, 0) << > ADLS_PSF_PT_SHIFT; > > + /* > + * If we already have the bw state then recompute everything > + * even if pipe data_rate / active_planes didn't change. > + * Other things (such as SAGV) may have changed. > + */ > + new_bw_state = intel_atomic_get_new_bw_state(state); > + > for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, > new_crtc_state, i) { > unsigned int old_data_rate = > -- > 2.34.1 >
