On Thu, Mar 03, 2022 at 02:37:35PM -0800, [email protected] wrote: > From: John Harrison <[email protected]> > > An earlier patch added support for compute engines. However, it missed > enabling the anti-pre-emption w/a for the new engine class. So move > the 'compute capable' flag earlier and use it for the pre-emption w/a > test. > > Fixes: c674c5b9342e ("drm/i915/xehp: CCS should use RCS setup functions") > Cc: Tvrtko Ursulin <[email protected]> > Cc: Daniele Ceraolo Spurio <[email protected]> > Cc: Aravind Iddamsetty <[email protected]> > Cc: Matt Roper <[email protected]> > Cc: Tvrtko Ursulin <[email protected]> > Cc: Daniel Vetter <[email protected]> > Cc: Maarten Lankhorst <[email protected]> > Cc: Lucas De Marchi <[email protected]> > Cc: John Harrison <[email protected]> > Cc: Jason Ekstrand <[email protected]> > Cc: "Michał Winiarski" <[email protected]> > Cc: Matthew Brost <[email protected]> > Cc: Chris Wilson <[email protected]> > Cc: Tejas Upadhyay <[email protected]> > Cc: Umesh Nerlige Ramappa <[email protected]> > Cc: "Thomas Hellström" <[email protected]> > Cc: Stuart Summers <[email protected]> > Cc: Matthew Auld <[email protected]> > Cc: Jani Nikula <[email protected]> > Cc: Ramalingam C <[email protected]> > Cc: Akeem G Abodunrin <[email protected]> > Signed-off-by: John Harrison <[email protected]>
Reviewed-by: Matt Roper <[email protected]> > --- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > index 22e70e4e007c..4185c7338581 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > @@ -421,6 +421,12 @@ static int intel_engine_setup(struct intel_gt *gt, enum > intel_engine_id id, > engine->logical_mask = BIT(logical_instance); > __sprint_engine_name(engine); > > + /* features common between engines sharing EUs */ > + if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) { > + engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE; > + engine->flags |= I915_ENGINE_HAS_EU_PRIORITY; > + } > + > engine->props.heartbeat_interval_ms = > CONFIG_DRM_I915_HEARTBEAT_INTERVAL; > engine->props.max_busywait_duration_ns = > @@ -433,15 +439,9 @@ static int intel_engine_setup(struct intel_gt *gt, enum > intel_engine_id id, > CONFIG_DRM_I915_TIMESLICE_DURATION; > > /* Override to uninterruptible for OpenCL workloads. */ > - if (GRAPHICS_VER(i915) == 12 && engine->class == RENDER_CLASS) > + if (GRAPHICS_VER(i915) == 12 && (engine->flags & > I915_ENGINE_HAS_RCS_REG_STATE)) > engine->props.preempt_timeout_ms = 0; > > - /* features common between engines sharing EUs */ > - if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) { > - engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE; > - engine->flags |= I915_ENGINE_HAS_EU_PRIORITY; > - } > - > /* Cap properties according to any system limits */ > #define CLAMP_PROP(field) \ > do { \ > -- > 2.25.1 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795
