On Tue, 03 May 2022, Ville Syrjala <[email protected]> wrote: > From: Ville Syrjälä <[email protected]> > > Currently we calculate a lot of things (pixel rate, watermarks, > cdclk) trusting that the DPLL can generate the exact frequency > we ask it. In practice that is not true and there can be > certain amount of rounding involved. > > To allow us to eventually get accurate numbers for all our > DPLL clock derived state we need to move the DPLL calculation > to hapen much earlier. To that end we hoist it up to the just > after the fastset checks. For now we just do the easy code > motion, and the actual back feeding of the final DPLL clock > into the state will come later. > > A slight change here is that now .crtc_compute_clock() > can get called while the shared_dpll is still assigned. > But since .crtc_compute_clock() no longer assignes new > shared_dplls this is perfectly fine. > > TODO: I'd actually like to do this before the fastset check > so that if the DPLL state should change we actually do the > modeset. Which I think is what the video aficionados want, > but it might not be what the fans of fastboot want. Not yet > sure how to reconcile those conflicting requirements... > > v2: s/return/goto/ in error handling > > Signed-off-by: Ville Syrjälä <[email protected]>
Reviewed-by: Jani Nikula <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_display.c | 9 +++++---- > drivers/gpu/drm/i915/display/intel_dpll.c | 3 --- > 2 files changed, 5 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index 0decf3d24237..5e50e0d56088 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -4905,10 +4905,6 @@ static int intel_crtc_atomic_check(struct > intel_atomic_state *state, > crtc_state->update_wm_post = true; > > if (mode_changed) { > - ret = intel_dpll_crtc_compute_clock(state, crtc); > - if (ret) > - return ret; > - > ret = intel_dpll_crtc_get_shared_dpll(state, crtc); > if (ret) > return ret; > @@ -7801,6 +7797,11 @@ static int intel_atomic_check(struct drm_device *dev, > new_crtc_state, i) { > if (intel_crtc_needs_modeset(new_crtc_state)) { > any_ms = true; > + > + ret = intel_dpll_crtc_compute_clock(state, crtc); > + if (ret) > + goto fail; > + > continue; > } > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c > b/drivers/gpu/drm/i915/display/intel_dpll.c > index c19fb075ee6e..7f0538ee2b51 100644 > --- a/drivers/gpu/drm/i915/display/intel_dpll.c > +++ b/drivers/gpu/drm/i915/display/intel_dpll.c > @@ -1449,9 +1449,6 @@ int intel_dpll_crtc_compute_clock(struct > intel_atomic_state *state, > > drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state)); > > - if (drm_WARN_ON(&i915->drm, crtc_state->shared_dpll)) > - return 0; > - > memset(&crtc_state->dpll_hw_state, 0, > sizeof(crtc_state->dpll_hw_state)); -- Jani Nikula, Intel Open Source Graphics Center
