[Intel-gfx] [PATCH] drm/i915/dg1: Fix power gate sequence.

[Rodrigo Vivi]

sub-pipe PG is not present on DG1. Setting these bits can disable
other power gates and cause GPU hangs on video playbacks.

HSDES: 1507666497, 1407222020
VLK: 16314, 4304

Fixes: 85a12d7eb8fe ("drm/i915/tgl: Fix Media power gate sequence.")
Cc: Matt Roper <matthew.d.ro...@intel.com>
Cc: Ashutosh Dixit <ashutosh.di...@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_rc6.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c 
b/drivers/gpu/drm/i915/gt/intel_rc6.c
index f8d0523f4c18..d1dcb018117d 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -134,7 +134,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
                        GEN9_MEDIA_PG_ENABLE |
                        GEN11_MEDIA_SAMPLER_PG_ENABLE;
 
-       if (GRAPHICS_VER(gt->i915) >= 12) {
+       if (GRAPHICS_VER(gt->i915) >= 12 && !IS_DG1(gt->i915)) {
                for (i = 0; i < I915_MAX_VCS; i++)
                        if (HAS_ENGINE(gt, _VCS(i)))
                                pg_enable |= (VDN_HCP_POWERGATE_ENABLE(i) |
-- 
2.35.3