From: Ville Syrjälä <[email protected]> On FBC2 (CTG+) page flips will automagically nuke FBC, so the only thing we need to do on page flip is update the CPU fence information.
On FBC1 we need to to disable+re-enable FBC around page flips. Previously we just called intel_disable_fbc() + intel_update_fbc() to do that. However intel_update_fbc() would actually need to grab all the modeset locks, which we can't do from the driver workqueue. Make things a bit more straightforward by simply disabling FBC only if it's active/scheduled to be active on the current CRTC, and restart it on the same CRTC after the flip. FIXME: Several FBC1 docs actually seem to indicate that sync flips will also cause a nuke on FBC1. Need to verify this. Signed-off-by: Ville Syrjälä <[email protected]> --- drivers/gpu/drm/i915/intel_display.c | 5 +- drivers/gpu/drm/i915/intel_drv.h | 4 ++ drivers/gpu/drm/i915/intel_pm.c | 96 +++++++++++++++++++++++++++++++++++- 3 files changed, 102 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 4155814..af0eafe 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -8222,7 +8222,7 @@ static void intel_unpin_work_fn(struct work_struct *__work) drm_gem_object_unreference(&work->pending_flip_obj->base); drm_gem_object_unreference(&work->old_fb_obj->base); - intel_update_fbc(dev); + intel_fbc_flip_end(work->crtc, work->crtc->fb); mutex_unlock(&dev->struct_mutex); BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); @@ -8661,7 +8661,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, if (ret) goto cleanup_pending; - intel_disable_fbc(dev); + intel_fbc_flip_start(crtc, fb); + intel_mark_fb_busy(obj, NULL); mutex_unlock(&dev->struct_mutex); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 119bb95..f9e9ca0 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -836,6 +836,10 @@ void intel_update_sprite_watermarks(struct drm_plane *plane, bool enabled, bool scaled); void intel_init_pm(struct drm_device *dev); bool intel_fbc_enabled(struct drm_device *dev); +void intel_fbc_flip_start(struct drm_crtc *crtc, + struct drm_framebuffer *fb); +void intel_fbc_flip_end(struct drm_crtc *crtc, + struct drm_framebuffer *fb); void intel_update_fbc(struct drm_device *dev); void intel_gpu_ips_init(struct drm_i915_private *dev_priv); void intel_gpu_ips_teardown(void); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 4039aa3..2a613ac 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -363,6 +363,8 @@ static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval) if (!dev_priv->display.enable_fbc) return; + WARN_ON(dev_priv->fbc.fbc_work && dev_priv->fbc.plane != -1); + intel_cancel_fbc_work(dev_priv); work = kzalloc(sizeof(*work), GFP_KERNEL); @@ -401,6 +403,8 @@ void intel_disable_fbc(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; + WARN_ON(dev_priv->fbc.fbc_work && dev_priv->fbc.plane != -1); + intel_cancel_fbc_work(dev_priv); if (!dev_priv->display.disable_fbc) @@ -414,6 +418,96 @@ void intel_disable_fbc(struct drm_device *dev) } } +static void intel_update_fbc_fb(struct drm_crtc *crtc, + struct drm_framebuffer *fb) +{ + struct drm_device *dev = crtc->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_fbc_work *work = dev_priv->fbc.fbc_work; + + /* + * If we've just scheduled an fbc work, + * simply update the fb for the work. + */ + if (work) { + WARN_ON(dev_priv->fbc.plane != -1); + + if (work->crtc != crtc) + return; + + drm_framebuffer_reference(fb); + drm_framebuffer_unreference(work->fb); + work->fb = fb; + } + + if (dev_priv->fbc.plane == to_intel_crtc(crtc)->plane) { + WARN_ON(dev_priv->fbc.fbc_work); + + if (dev_priv->fbc.fb == fb && + dev_priv->fbc.y == crtc->y) + return; + + intel_setup_fbc(crtc, fb, 500); + } +} + +void intel_fbc_flip_start(struct drm_crtc *crtc, + struct drm_framebuffer *fb) +{ + struct drm_device *dev = crtc->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_fbc_work *work = dev_priv->fbc.fbc_work; + + if (!I915_HAS_FBC(dev)) + return; + + WARN_ON(work && dev_priv->fbc.plane != -1); + + /* just need to update the CPU fence on FBC2 */ + if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { + intel_update_fbc_fb(crtc, fb); + return; + } + + if (work && work->crtc == crtc) { + intel_cancel_fbc_work(dev_priv); + + /* + * set fbc.plane so that we can re-enable + * FBC with just intel_fbc_flip_end(). + */ + dev_priv->fbc.plane = to_intel_crtc(crtc)->plane; + return; + } + + if (dev_priv->fbc.plane == to_intel_crtc(crtc)->plane) { + dev_priv->display.disable_fbc(dev); + + /* + * don't clear fbc.plane so that we can + * re-enable FBC with just intel_fbc_flip_end(). + */ + } +} + +void intel_fbc_flip_end(struct drm_crtc *crtc, + struct drm_framebuffer *fb) +{ + struct drm_device *dev = crtc->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + + if (!I915_HAS_FBC(dev)) + return; + + WARN_ON(dev_priv->fbc.fbc_work && dev_priv->fbc.plane != -1); + + /* nothing to do on FBC2 */ + if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) + return; + + intel_update_fbc_fb(crtc, fb); +} + static bool set_no_fbc_reason(struct drm_i915_private *dev_priv, enum no_fbc_reason reason) { @@ -567,7 +661,7 @@ void intel_update_fbc(struct drm_device *dev) dev_priv->fbc.y == crtc->y) return; - if (intel_fbc_enabled(dev)) { + if (intel_fbc_enabled(dev) || dev_priv->fbc.plane != -1) { /* We update FBC along two paths, after changing fb/crtc * configuration (modeswitching) and after page-flipping * finishes. For the latter, we know that not only did -- 1.8.3.2 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
