For these types of display buffers, we need to able to CPU access some
part of the backing memory in prepare_plane_clear_colors(). As a result
we need to ensure we always place in the mappable part of lmem, which
becomes necessary on small-bar systems.
v2(Nirmoy & Ville):
- Add some commentary for why we need to CPU access the buffer.
- Split out the other changes, so we just consider the display change
here.
v3:
- Handle this in the dpt path.
v4(Ville):
- Drop the intel_fb_rc_ccs_cc_plane() sanity check in
pin_and_fence_fb_obj(), since we can also trigger this on DG1 it
seems.
Fixes: eb1c535f0d69 ("drm/i915: turn on small BAR support")
Reported-by: Jianshui Yu <[email protected]>
Signed-off-by: Matthew Auld <[email protected]>
Cc: Ville Syrjälä <[email protected]>
Cc: Nirmoy Das <[email protected]>
---
drivers/gpu/drm/i915/display/intel_fb_pin.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c
b/drivers/gpu/drm/i915/display/intel_fb_pin.c
index 5031ee5695dd..e12339f46640 100644
--- a/drivers/gpu/drm/i915/display/intel_fb_pin.c
+++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c
@@ -50,7 +50,18 @@ intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
continue;
if (HAS_LMEM(dev_priv)) {
- ret = i915_gem_object_migrate(obj, &ww,
INTEL_REGION_LMEM_0);
+ unsigned int flags = obj->flags;
+
+ /*
+ * For this type of buffer we need to able to read from
the CPU
+ * the clear color value found in the buffer, hence we
need to
+ * ensure it is always in the mappable part of lmem, if
this is
+ * a small-bar device.
+ */
+ if (intel_fb_rc_ccs_cc_plane(fb) >= 0)
+ flags &= ~I915_BO_ALLOC_GPU_ONLY;
+ ret = __i915_gem_object_migrate(obj, &ww,
INTEL_REGION_LMEM_0,
+ flags);
if (ret)
continue;
}
--
2.37.3
