From: Jigar Bhatt <[email protected]> Due to RTL bug FBC cannot be enabled when pipe is programed in Pixel Extension mode of Zero Extend. This caused 1 bit change in pixel value in compressed vs uncompressed frame which comes up as a flicker. WA for D13 is to always used MSB Extend for Pixel extension.
WA: 16015082434 Signed-off-by: Jigar Bhatt <[email protected]> Signed-off-by: Animesh Manna <[email protected]> --- drivers/gpu/drm/i915/display/intel_display.c | 4 +++- drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 5a386c7c0bc9..7006c1cb09f7 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -3374,8 +3374,10 @@ static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state) if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state)) val |= PIPE_MISC_HDR_MODE_PRECISION; - if (DISPLAY_VER(dev_priv) >= 12) + if (DISPLAY_VER(dev_priv) >= 12) { val |= PIPE_MISC_PIXEL_ROUNDING_TRUNC; + val &= ~(PIPEMISC_PIXEL_EXTENSION_ZERO_EXTEND); + } intel_de_write(dev_priv, PIPE_MISC(crtc->pipe), val); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d22ffd7a32dc..dcad60b5f50e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3501,6 +3501,7 @@ #define PIPE_MISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */ #define PIPE_MISC_HDR_MODE_PRECISION REG_BIT(23) /* icl+ */ #define PIPE_MISC_OUTPUT_COLORSPACE_YUV REG_BIT(11) +#define PIPEMISC_PIXEL_EXTENSION_ZERO_EXTEND REG_BIT(9) #define PIPE_MISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */ /* * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with -- 2.29.0
