As per Bspec, Big Joiner BW check is:
Output bpp <= PPC * CDCLK frequency * Big joiner interface bits /
Pixel clock
Currently we always use max_cdclk in the check for both modevalid
and compute config steps.
During modevalid use max_cdclk_freq for the check.
During compute config step use current cdclk for the check.
Signed-off-by: Ankit Nautiyal <ankit.k.nauti...@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 9 ++++++---
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 1 +
3 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 3fe651a8f5d0..d6600de1ab49 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -711,6 +711,7 @@ u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private
*i915, u32 bpp, u32 p
u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
u32 link_clock, u32 lane_count,
u32 mode_clock, u32 mode_hdisplay,
+ unsigned int cdclk,
bool bigjoiner,
u32 pipe_bpp,
u32 timeslots)
@@ -757,9 +758,9 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private
*i915,
if (bigjoiner) {
int bigjoiner_interface_bits = DISPLAY_VER(i915) <= 12 ? 24 :
36;
- u32 max_bpp_bigjoiner =
- i915->display.cdclk.max_cdclk_freq * 2 *
bigjoiner_interface_bits /
- intel_dp_mode_to_fec_clock(mode_clock);
+
+ u32 max_bpp_bigjoiner = cdclk * 2 * bigjoiner_interface_bits /
+ intel_dp_mode_to_fec_clock(mode_clock);
bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
}
@@ -1073,6 +1074,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
max_lanes,
target_clock,
mode->hdisplay,
+
dev_priv->display.cdclk.max_cdclk_freq,
bigjoiner,
pipe_bpp, 64) >> 4;
dsc_slice_count =
@@ -1580,6 +1582,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_config->lane_count,
adjusted_mode->crtc_clock,
adjusted_mode->crtc_hdisplay,
+
dev_priv->display.cdclk.hw.cdclk,
pipe_config->bigjoiner_pipes,
pipe_bpp,
timeslots);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
b/drivers/gpu/drm/i915/display/intel_dp.h
index ef39e4f7a329..d150bfe8abf4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -106,6 +106,7 @@ int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8
dsc_max_bpc);
u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
u32 link_clock, u32 lane_count,
u32 mode_clock, u32 mode_hdisplay,
+ unsigned int cdclk,
bool bigjoiner,
u32 pipe_bpp,
u32 timeslots);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index a860cbc5dbea..266e31b78729 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -925,6 +925,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
max_lanes,
target_clock,
mode->hdisplay,
+
dev_priv->display.cdclk.max_cdclk_freq,
bigjoiner,
pipe_bpp, 64) >> 4;
dsc_slice_count =
--
2.25.1
