Hi Manasi, > -----Original Message----- > From: Intel-gfx <[email protected]> On Behalf Of Manasi > Navare > Sent: 12 August 2023 02:35 > To: [email protected] > Cc: Drew Davenport <[email protected]>; Sean Paul > <[email protected]> > Subject: [Intel-gfx] [PATCH v2] drm/i915/display: Dual refresh rate fastset > fixes > with VRR fastset > > Dual refresh rate (DRR) fastset seamlessly lets refresh rate throttle without > needing a full modeset. > However with the recent VRR fastset patches that got merged this logic was > broken. This is broken because now with VRR fastset VRR parameters are > calculated by default at the nominal refresh rate say 120Hz. > Now when DRR throttle happens to switch refresh rate to 60Hz, crtc clock > changes and this throws a mismatch in VRR parameters and fastset logic for > DRR gets thrown off and full modeset is indicated. > > This patch fixes this by ignoring the pipe mismatch for VRR parameters in the > case of DRR and when VRR is not enabled. With this fix, DRR will still > throttle > seamlessly as long as VRR is not enabled. > > This will still need a full modeset for both DRR and VRR operating together > during the refresh rate throttle and then enabling VRR since now VRR > parameters need to be recomputed with new crtc clock and written to HW. > > This DRR + VRR fastset in conjunction needs more work in the driver and will > be fixed in later patches. > > v2: > Check for pipe config mismatch in crtc clock whenever VRR is enabled > > Cc: Drew Davenport <[email protected]> > Cc: Ville Syrjälä <[email protected]> > Cc: Sean Paul <[email protected]> > Signed-off-by: Manasi Navare <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_display.c | 14 ++++++++------ > 1 file changed, 8 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index 763ab569d8f3..efc407e11d8e 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -5352,7 +5352,7 @@ intel_pipe_config_compare(const struct > intel_crtc_state *current_config, > if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5) > PIPE_CONF_CHECK_I(pipe_bpp); > > - if (!fastset || !pipe_config->seamless_m_n) { > + if (!fastset || !pipe_config->seamless_m_n || pipe_config->vrr.enable) > +{ > PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock); > PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock); > } > @@ -5387,11 +5387,13 @@ intel_pipe_config_compare(const struct > intel_crtc_state *current_config, > > if (!fastset) > PIPE_CONF_CHECK_BOOL(vrr.enable); > - PIPE_CONF_CHECK_I(vrr.vmin); > - PIPE_CONF_CHECK_I(vrr.vmax); > - PIPE_CONF_CHECK_I(vrr.flipline); > - PIPE_CONF_CHECK_I(vrr.pipeline_full); > - PIPE_CONF_CHECK_I(vrr.guardband); > + if ((!fastset && !pipe_config->seamless_m_n) || pipe_config- > >vrr.enable) { > + PIPE_CONF_CHECK_I(vrr.vmin); > + PIPE_CONF_CHECK_I(vrr.vmax); > + PIPE_CONF_CHECK_I(vrr.flipline); > + PIPE_CONF_CHECK_I(vrr.pipeline_full); > + PIPE_CONF_CHECK_I(vrr.guardband); > + }
It appears that when switching to the fixed refresh rate mode, such as the 60HZ mode, the vrr.* parameters are also being changed. However after implementing the change above, a pipe state mismatch occurs during the 'intel_modeset_verify_crtc' process. I think this occurs because we are avoiding 'PIPE_CONF_CHECK' to prevent a complete modeset ? Considering this would it be feasible to skip checking the aforementioned pipe configuration during fixed refresh rate mode and only compare them when we enable VRR ? > > #undef PIPE_CONF_CHECK_X > #undef PIPE_CONF_CHECK_I > -- > 2.41.0.640.ga95def55d0-goog
